Decouple spi_clk from cpu_clk

hw/efinix_fpga/src/spi_controller.sv

@@ -1,5 +1,6 @@
 module spi_controller(
-    input i_clk,
+    input i_clk_cpu,
+    input i_clk_50,
     input i_rst,
 
     input i_cs,
@@ -37,7 +38,9 @@ assign o_spi_cs = ~r_control[0];
 assign o_spi_clk = spi_clk;
 assign o_spi_mosi = r_spi_mosi;
 
-always @(negedge i_clk) begin
+logic working;
+
+always @(negedge i_clk_cpu) begin
     if (i_rst) begin
         r_baud_rate <= 8'h1;
         r_input_data <= '0;
@@ -48,6 +51,7 @@ always @(negedge i_clk) begin
         spi_clk <= '0;
         active <= '0;
     end else begin
+        active <= '0;
         if (~i_rwb & i_cs) begin
             unique case (i_addr)
                 0: r_baud_rate <= i_data;
@@ -59,28 +63,38 @@ always @(negedge i_clk) begin
                 3: r_control <= i_data;
             endcase
         end
+        working <= active_f;
+    end
 
-        if (active) begin
+end
-            r_spi_mosi <= r_output_data[7];
+
-            r_clock_counter <= r_clock_counter + 9'b1;
+logic active_f;
-            if (r_clock_counter >= r_baud_rate) begin
+logic [7:0] r_output_data_f;
-                r_clock_counter <= '0;
+
-                spi_clk <= ~spi_clk;
+
-                // rising edge
+always @(posedge i_clk_50) begin
-                if (spi_clk == '0) begin
+    if (active_f) begin
-                    r_output_data <= r_output_data << 1;
+        r_spi_mosi <= r_output_data_f[7];
-                    count <= count + 1;
+        r_clock_counter <= r_clock_counter + 9'b1;
-                end
+        if (r_clock_counter >= r_baud_rate) begin
-                // falling edge
+            r_clock_counter <= '0;
-                if (spi_clk == '1) begin
+            spi_clk <= ~spi_clk;
-                    r_input_data <= {r_input_data[6:0], i_spi_miso};
+            // rising edge
-                    if (count == '0) begin
+            if (spi_clk == '0) begin
-                        active <= '0;
+                r_output_data_f <= r_output_data_f << 1;
-                    end
+                count <= count + 1;
+            end
+            // falling edge
+            if (spi_clk == '1) begin
+                r_input_data <= {r_input_data[6:0], i_spi_miso};
+                if (count == '0) begin
+                    active_f <= '0;
                 end
             end
-
         end
+    end else begin
+        r_output_data_f <= r_output_data;
+        active_f <= active;
     end
 end
 
@@ -89,7 +103,7 @@ always_comb begin
         0: o_data = r_baud_rate;
         1: o_data = r_input_data;
         2:;
-        3: o_data = {active, r_control[6:0]};
+        3: o_data = {working, r_control[6:0]};
         default: o_data = 'x;
     endcase
 end

hw/efinix_fpga/src/super6502.sv

@@ -250,7 +250,8 @@ uart_wrapper u_uart(
 assign w_int_in[1] = w_uart_irq;
 
 spi_controller spi_controller(
-    .i_clk(clk_cpu),
+    .i_clk_cpu(clk_cpu),
+    .i_clk_50(clk_50),
     .i_rst(~cpu_resb),
     .i_cs(w_spi_cs),
     .i_rwb(cpu_rwb),