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Create quartus project

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Byron Lathi
2022-03-05 17:52:42 -06:00
parent b996d93c99
commit aca17a9cf8
10 changed files with 3761 additions and 1 deletions
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hw/fpga/simulation/modelsim/super6502.sft Normal file
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set tool_name "ModelSim-Altera (SystemVerilog)"