Create quartus project
This commit is contained in:
Byron Lathi
16
hw/fpga/greybox_tmp/cbx_args.txt
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16
hw/fpga/greybox_tmp/cbx_args.txt
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@@ -0,0 +1,16 @@
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CLOCK_ENABLE_INPUT_A=BYPASS
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CLOCK_ENABLE_OUTPUT_A=BYPASS
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INTENDED_DEVICE_FAMILY="MAX 10"
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NUMWORDS_A=32768
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OPERATION_MODE=SINGLE_PORT
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OUTDATA_ACLR_A=NONE
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OUTDATA_REG_A=UNREGISTERED
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POWER_UP_UNINITIALIZED=FALSE
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READ_DURING_WRITE_MODE_PORT_A=NEW_DATA_NO_NBE_READ
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WIDTHAD_A=15
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WIDTH_A=8
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WIDTH_BYTEENA_A=1
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DEVICE_FAMILY="MAX 10"
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address_a
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clock0
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q_a
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1
hw/fpga/output_files/super6502.sld
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1
hw/fpga/output_files/super6502.sld
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@@ -0,0 +1 @@
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<sld_project_info/>
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4
hw/fpga/ram.qip
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4
hw/fpga/ram.qip
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@@ -0,0 +1,4 @@
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set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT"
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set_global_assignment -name IP_TOOL_VERSION "18.1"
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set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}"
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "ram.v"]
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172
hw/fpga/ram.v
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172
hw/fpga/ram.v
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@@ -0,0 +1,172 @@
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// megafunction wizard: %RAM: 1-PORT%
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// GENERATION: STANDARD
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// VERSION: WM1.0
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// MODULE: altsyncram
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// ============================================================
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// File Name: ram.v
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// Megafunction Name(s):
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// altsyncram
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//
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// Simulation Library Files(s):
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// altera_mf
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// ============================================================
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// ************************************************************
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// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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//
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// 18.1.0 Build 625 09/12/2018 SJ Lite Edition
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// ************************************************************
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//Copyright (C) 2018 Intel Corporation. All rights reserved.
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//Your use of Intel Corporation's design tools, logic functions
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//and other software and tools, and its AMPP partner logic
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//functions, and any output files from any of the foregoing
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//(including device programming or simulation files), and any
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//associated documentation or information are expressly subject
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//to the terms and conditions of the Intel Program License
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//Subscription Agreement, the Intel Quartus Prime License Agreement,
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//the Intel FPGA IP License Agreement, or other applicable license
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//agreement, including, without limitation, that your use is for
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//the sole purpose of programming logic devices manufactured by
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//Intel and sold by Intel or its authorized distributors. Please
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//refer to the applicable agreement for further details.
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// synopsys translate_off
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`timescale 1 ps / 1 ps
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// synopsys translate_on
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module ram (
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address,
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clock,
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data,
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wren,
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q);
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input [14:0] address;
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input clock;
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input [7:0] data;
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input wren;
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output [7:0] q;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_off
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`endif
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tri1 clock;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_on
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`endif
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wire [7:0] sub_wire0;
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wire [7:0] q = sub_wire0[7:0];
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altsyncram altsyncram_component (
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.address_a (address),
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.clock0 (clock),
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.data_a (data),
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.wren_a (wren),
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.q_a (sub_wire0),
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.aclr0 (1'b0),
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.aclr1 (1'b0),
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.address_b (1'b1),
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.addressstall_a (1'b0),
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.addressstall_b (1'b0),
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.byteena_a (1'b1),
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.byteena_b (1'b1),
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.clock1 (1'b1),
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.clocken0 (1'b1),
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.clocken1 (1'b1),
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.clocken2 (1'b1),
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.clocken3 (1'b1),
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.data_b (1'b1),
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.eccstatus (),
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.q_b (),
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.rden_a (1'b1),
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.rden_b (1'b1),
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.wren_b (1'b0));
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defparam
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altsyncram_component.clock_enable_input_a = "BYPASS",
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altsyncram_component.clock_enable_output_a = "BYPASS",
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altsyncram_component.intended_device_family = "MAX 10",
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altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
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altsyncram_component.lpm_type = "altsyncram",
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altsyncram_component.numwords_a = 32768,
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altsyncram_component.operation_mode = "SINGLE_PORT",
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altsyncram_component.outdata_aclr_a = "NONE",
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altsyncram_component.outdata_reg_a = "UNREGISTERED",
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altsyncram_component.power_up_uninitialized = "FALSE",
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altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
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altsyncram_component.widthad_a = 15,
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altsyncram_component.width_a = 8,
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altsyncram_component.width_byteena_a = 1;
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endmodule
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// ============================================================
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// CNX file retrieval info
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// ============================================================
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// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
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// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
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// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
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// Retrieval info: PRIVATE: AclrData NUMERIC "0"
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// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
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// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
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// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
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// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
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// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
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// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
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// Retrieval info: PRIVATE: Clken NUMERIC "0"
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// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
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// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
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// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
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// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
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// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10"
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// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
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// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
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// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
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// Retrieval info: PRIVATE: MIFfilename STRING ""
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// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "32768"
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// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
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// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
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// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
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// Retrieval info: PRIVATE: RegData NUMERIC "1"
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// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
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// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
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// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
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// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
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// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
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// Retrieval info: PRIVATE: WidthAddr NUMERIC "15"
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// Retrieval info: PRIVATE: WidthData NUMERIC "8"
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// Retrieval info: PRIVATE: rden NUMERIC "0"
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// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
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// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
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// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
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// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10"
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// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
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// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
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// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32768"
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// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
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// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
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// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
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// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
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// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
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// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "15"
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// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
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// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
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// Retrieval info: USED_PORT: address 0 0 15 0 INPUT NODEFVAL "address[14..0]"
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// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
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// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
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// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
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// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
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// Retrieval info: CONNECT: @address_a 0 0 15 0 address 0 0 15 0
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// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
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// Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
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// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
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// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
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// Retrieval info: GEN_FILE: TYPE_NORMAL ram.v TRUE
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// Retrieval info: GEN_FILE: TYPE_NORMAL ram.inc FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL ram.cmp FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL ram.bsf FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL ram_inst.v FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL ram_bb.v FALSE
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// Retrieval info: LIB_FILE: altera_mf
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1
hw/fpga/simulation/modelsim/super6502.sft
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1
hw/fpga/simulation/modelsim/super6502.sft
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@@ -0,0 +1 @@
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set tool_name "ModelSim-Altera (SystemVerilog)"
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3313
hw/fpga/simulation/modelsim/super6502.svo
Normal file
3313
hw/fpga/simulation/modelsim/super6502.svo
Normal file
File diff suppressed because it is too large
Load Diff
145
hw/fpga/simulation/modelsim/super6502_modelsim.xrf
Normal file
145
hw/fpga/simulation/modelsim/super6502_modelsim.xrf
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@@ -0,0 +1,145 @@
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vendor_name = ModelSim
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source_file = 1, /home/byron/Projects/super6502/hw/fpga/super6502.sv
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source_file = 1, /home/byron/Projects/super6502/hw/fpga/ram.qip
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source_file = 1, /home/byron/Projects/super6502/hw/fpga/ram.v
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source_file = 1, /home/byron/Projects/super6502/hw/fpga/super6502.sdc
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source_file = 1, /software/quartus-lite-18.1/quartus/libraries/megafunctions/altsyncram.tdf
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source_file = 1, /software/quartus-lite-18.1/quartus/libraries/megafunctions/stratix_ram_block.inc
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source_file = 1, /software/quartus-lite-18.1/quartus/libraries/megafunctions/lpm_mux.inc
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source_file = 1, /software/quartus-lite-18.1/quartus/libraries/megafunctions/lpm_decode.inc
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source_file = 1, /software/quartus-lite-18.1/quartus/libraries/megafunctions/aglobal181.inc
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source_file = 1, /software/quartus-lite-18.1/quartus/libraries/megafunctions/a_rdenreg.inc
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source_file = 1, /software/quartus-lite-18.1/quartus/libraries/megafunctions/altrom.inc
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source_file = 1, /software/quartus-lite-18.1/quartus/libraries/megafunctions/altram.inc
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source_file = 1, /software/quartus-lite-18.1/quartus/libraries/megafunctions/altdpram.inc
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source_file = 1, /software/quartus-lite-18.1/quartus/libraries/megafunctions/cbx.lst
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source_file = 1, /home/byron/Projects/super6502/hw/fpga/db/altsyncram_okf1.tdf
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source_file = 1, /home/byron/Projects/super6502/hw/fpga/db/decode_c7a.tdf
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source_file = 1, /home/byron/Projects/super6502/hw/fpga/db/decode_5j9.tdf
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source_file = 1, /home/byron/Projects/super6502/hw/fpga/db/mux_s1b.tdf
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design_name = super6502
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instance = comp, \~QUARTUS_CREATED_GND~I , ~QUARTUS_CREATED_GND~I, super6502, 1
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instance = comp, \cpu_data[0]~output , cpu_data[0]~output, super6502, 1
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instance = comp, \cpu_data[1]~output , cpu_data[1]~output, super6502, 1
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instance = comp, \cpu_data[2]~output , cpu_data[2]~output, super6502, 1
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instance = comp, \cpu_data[3]~output , cpu_data[3]~output, super6502, 1
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instance = comp, \cpu_data[4]~output , cpu_data[4]~output, super6502, 1
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instance = comp, \cpu_data[5]~output , cpu_data[5]~output, super6502, 1
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instance = comp, \cpu_data[6]~output , cpu_data[6]~output, super6502, 1
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instance = comp, \cpu_data[7]~output , cpu_data[7]~output, super6502, 1
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instance = comp, \cpu_led~output , cpu_led~output, super6502, 1
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instance = comp, \cpu_resb~output , cpu_resb~output, super6502, 1
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instance = comp, \cpu_rdy~output , cpu_rdy~output, super6502, 1
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instance = comp, \cpu_sob~output , cpu_sob~output, super6502, 1
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instance = comp, \cpu_irqb~output , cpu_irqb~output, super6502, 1
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instance = comp, \cpu_phi2~output , cpu_phi2~output, super6502, 1
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instance = comp, \cpu_be~output , cpu_be~output, super6502, 1
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instance = comp, \cpu_nmib~output , cpu_nmib~output, super6502, 1
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instance = comp, \clk~input , clk~input, super6502, 1
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instance = comp, \clk~inputclkctrl , clk~inputclkctrl, super6502, 1
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instance = comp, \cpu_addr[13]~input , cpu_addr[13]~input, super6502, 1
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instance = comp, \main_memory|altsyncram_component|auto_generated|address_reg_a[0] , main_memory|altsyncram_component|auto_generated|address_reg_a[0], super6502, 1
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instance = comp, \cpu_addr[14]~input , cpu_addr[14]~input, super6502, 1
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instance = comp, \cpu_rwb~input , cpu_rwb~input, super6502, 1
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instance = comp, \main_memory|altsyncram_component|auto_generated|decode3|w_anode236w[2]~0 , main_memory|altsyncram_component|auto_generated|decode3|w_anode236w[2]~0, super6502, 1
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instance = comp, \main_memory|altsyncram_component|auto_generated|rden_decode|w_anode275w[2]~0 , main_memory|altsyncram_component|auto_generated|rden_decode|w_anode275w[2]~0, super6502, 1
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instance = comp, \cpu_data[0]~input , cpu_data[0]~input, super6502, 1
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instance = comp, \cpu_addr[0]~input , cpu_addr[0]~input, super6502, 1
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instance = comp, \cpu_addr[1]~input , cpu_addr[1]~input, super6502, 1
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||||
instance = comp, \cpu_addr[2]~input , cpu_addr[2]~input, super6502, 1
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instance = comp, \cpu_addr[3]~input , cpu_addr[3]~input, super6502, 1
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instance = comp, \cpu_addr[4]~input , cpu_addr[4]~input, super6502, 1
|
||||
instance = comp, \cpu_addr[5]~input , cpu_addr[5]~input, super6502, 1
|
||||
instance = comp, \cpu_addr[6]~input , cpu_addr[6]~input, super6502, 1
|
||||
instance = comp, \cpu_addr[7]~input , cpu_addr[7]~input, super6502, 1
|
||||
instance = comp, \cpu_addr[8]~input , cpu_addr[8]~input, super6502, 1
|
||||
instance = comp, \cpu_addr[9]~input , cpu_addr[9]~input, super6502, 1
|
||||
instance = comp, \cpu_addr[10]~input , cpu_addr[10]~input, super6502, 1
|
||||
instance = comp, \cpu_addr[11]~input , cpu_addr[11]~input, super6502, 1
|
||||
instance = comp, \cpu_addr[12]~input , cpu_addr[12]~input, super6502, 1
|
||||
instance = comp, \main_memory|altsyncram_component|auto_generated|ram_block1a8 , main_memory|altsyncram_component|auto_generated|ram_block1a8, super6502, 1
|
||||
instance = comp, \main_memory|altsyncram_component|auto_generated|decode3|w_anode223w[2] , main_memory|altsyncram_component|auto_generated|decode3|w_anode223w[2], super6502, 1
|
||||
instance = comp, \main_memory|altsyncram_component|auto_generated|rden_decode|w_anode261w[2]~0 , main_memory|altsyncram_component|auto_generated|rden_decode|w_anode261w[2]~0, super6502, 1
|
||||
instance = comp, \main_memory|altsyncram_component|auto_generated|ram_block1a0 , main_memory|altsyncram_component|auto_generated|ram_block1a0, super6502, 1
|
||||
instance = comp, \main_memory|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 , main_memory|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0, super6502, 1
|
||||
instance = comp, \main_memory|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 , main_memory|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0, super6502, 1
|
||||
instance = comp, \main_memory|altsyncram_component|auto_generated|ram_block1a16 , main_memory|altsyncram_component|auto_generated|ram_block1a16, super6502, 1
|
||||
instance = comp, \main_memory|altsyncram_component|auto_generated|address_reg_a[1] , main_memory|altsyncram_component|auto_generated|address_reg_a[1], super6502, 1
|
||||
instance = comp, \main_memory|altsyncram_component|auto_generated|mux2|result_node[0]~0 , main_memory|altsyncram_component|auto_generated|mux2|result_node[0]~0, super6502, 1
|
||||
instance = comp, \main_memory|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 , main_memory|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0, super6502, 1
|
||||
instance = comp, \main_memory|altsyncram_component|auto_generated|rden_decode|w_anode293w[2]~0 , main_memory|altsyncram_component|auto_generated|rden_decode|w_anode293w[2]~0, super6502, 1
|
||||
instance = comp, \main_memory|altsyncram_component|auto_generated|ram_block1a24 , main_memory|altsyncram_component|auto_generated|ram_block1a24, super6502, 1
|
||||
instance = comp, \main_memory|altsyncram_component|auto_generated|mux2|result_node[0]~1 , main_memory|altsyncram_component|auto_generated|mux2|result_node[0]~1, super6502, 1
|
||||
instance = comp, \cpu_data[1]~input , cpu_data[1]~input, super6502, 1
|
||||
instance = comp, \main_memory|altsyncram_component|auto_generated|ram_block1a25 , main_memory|altsyncram_component|auto_generated|ram_block1a25, super6502, 1
|
||||
instance = comp, \main_memory|altsyncram_component|auto_generated|ram_block1a1 , main_memory|altsyncram_component|auto_generated|ram_block1a1, super6502, 1
|
||||
instance = comp, \main_memory|altsyncram_component|auto_generated|ram_block1a9 , main_memory|altsyncram_component|auto_generated|ram_block1a9, super6502, 1
|
||||
instance = comp, \main_memory|altsyncram_component|auto_generated|mux2|result_node[1]~2 , main_memory|altsyncram_component|auto_generated|mux2|result_node[1]~2, super6502, 1
|
||||
instance = comp, \main_memory|altsyncram_component|auto_generated|ram_block1a17 , main_memory|altsyncram_component|auto_generated|ram_block1a17, super6502, 1
|
||||
instance = comp, \main_memory|altsyncram_component|auto_generated|mux2|result_node[1]~3 , main_memory|altsyncram_component|auto_generated|mux2|result_node[1]~3, super6502, 1
|
||||
instance = comp, \cpu_data[2]~input , cpu_data[2]~input, super6502, 1
|
||||
instance = comp, \main_memory|altsyncram_component|auto_generated|ram_block1a18 , main_memory|altsyncram_component|auto_generated|ram_block1a18, super6502, 1
|
||||
instance = comp, \main_memory|altsyncram_component|auto_generated|ram_block1a2 , main_memory|altsyncram_component|auto_generated|ram_block1a2, super6502, 1
|
||||
instance = comp, \main_memory|altsyncram_component|auto_generated|mux2|result_node[2]~4 , main_memory|altsyncram_component|auto_generated|mux2|result_node[2]~4, super6502, 1
|
||||
instance = comp, \main_memory|altsyncram_component|auto_generated|ram_block1a26 , main_memory|altsyncram_component|auto_generated|ram_block1a26, super6502, 1
|
||||
instance = comp, \main_memory|altsyncram_component|auto_generated|ram_block1a10 , main_memory|altsyncram_component|auto_generated|ram_block1a10, super6502, 1
|
||||
instance = comp, \main_memory|altsyncram_component|auto_generated|mux2|result_node[2]~5 , main_memory|altsyncram_component|auto_generated|mux2|result_node[2]~5, super6502, 1
|
||||
instance = comp, \cpu_data[3]~input , cpu_data[3]~input, super6502, 1
|
||||
instance = comp, \main_memory|altsyncram_component|auto_generated|ram_block1a3 , main_memory|altsyncram_component|auto_generated|ram_block1a3, super6502, 1
|
||||
instance = comp, \main_memory|altsyncram_component|auto_generated|ram_block1a11 , main_memory|altsyncram_component|auto_generated|ram_block1a11, super6502, 1
|
||||
instance = comp, \main_memory|altsyncram_component|auto_generated|mux2|result_node[3]~6 , main_memory|altsyncram_component|auto_generated|mux2|result_node[3]~6, super6502, 1
|
||||
instance = comp, \main_memory|altsyncram_component|auto_generated|ram_block1a19 , main_memory|altsyncram_component|auto_generated|ram_block1a19, super6502, 1
|
||||
instance = comp, \main_memory|altsyncram_component|auto_generated|ram_block1a27 , main_memory|altsyncram_component|auto_generated|ram_block1a27, super6502, 1
|
||||
instance = comp, \main_memory|altsyncram_component|auto_generated|mux2|result_node[3]~7 , main_memory|altsyncram_component|auto_generated|mux2|result_node[3]~7, super6502, 1
|
||||
instance = comp, \cpu_data[4]~input , cpu_data[4]~input, super6502, 1
|
||||
instance = comp, \main_memory|altsyncram_component|auto_generated|ram_block1a12 , main_memory|altsyncram_component|auto_generated|ram_block1a12, super6502, 1
|
||||
instance = comp, \main_memory|altsyncram_component|auto_generated|ram_block1a28 , main_memory|altsyncram_component|auto_generated|ram_block1a28, super6502, 1
|
||||
instance = comp, \main_memory|altsyncram_component|auto_generated|ram_block1a4 , main_memory|altsyncram_component|auto_generated|ram_block1a4, super6502, 1
|
||||
instance = comp, \main_memory|altsyncram_component|auto_generated|ram_block1a20 , main_memory|altsyncram_component|auto_generated|ram_block1a20, super6502, 1
|
||||
instance = comp, \main_memory|altsyncram_component|auto_generated|mux2|result_node[4]~8 , main_memory|altsyncram_component|auto_generated|mux2|result_node[4]~8, super6502, 1
|
||||
instance = comp, \main_memory|altsyncram_component|auto_generated|mux2|result_node[4]~9 , main_memory|altsyncram_component|auto_generated|mux2|result_node[4]~9, super6502, 1
|
||||
instance = comp, \cpu_data[5]~input , cpu_data[5]~input, super6502, 1
|
||||
instance = comp, \main_memory|altsyncram_component|auto_generated|ram_block1a5 , main_memory|altsyncram_component|auto_generated|ram_block1a5, super6502, 1
|
||||
instance = comp, \main_memory|altsyncram_component|auto_generated|ram_block1a13 , main_memory|altsyncram_component|auto_generated|ram_block1a13, super6502, 1
|
||||
instance = comp, \main_memory|altsyncram_component|auto_generated|mux2|result_node[5]~10 , main_memory|altsyncram_component|auto_generated|mux2|result_node[5]~10, super6502, 1
|
||||
instance = comp, \main_memory|altsyncram_component|auto_generated|ram_block1a29 , main_memory|altsyncram_component|auto_generated|ram_block1a29, super6502, 1
|
||||
instance = comp, \main_memory|altsyncram_component|auto_generated|ram_block1a21 , main_memory|altsyncram_component|auto_generated|ram_block1a21, super6502, 1
|
||||
instance = comp, \main_memory|altsyncram_component|auto_generated|mux2|result_node[5]~11 , main_memory|altsyncram_component|auto_generated|mux2|result_node[5]~11, super6502, 1
|
||||
instance = comp, \cpu_data[6]~input , cpu_data[6]~input, super6502, 1
|
||||
instance = comp, \main_memory|altsyncram_component|auto_generated|ram_block1a22 , main_memory|altsyncram_component|auto_generated|ram_block1a22, super6502, 1
|
||||
instance = comp, \main_memory|altsyncram_component|auto_generated|ram_block1a6 , main_memory|altsyncram_component|auto_generated|ram_block1a6, super6502, 1
|
||||
instance = comp, \main_memory|altsyncram_component|auto_generated|mux2|result_node[6]~12 , main_memory|altsyncram_component|auto_generated|mux2|result_node[6]~12, super6502, 1
|
||||
instance = comp, \main_memory|altsyncram_component|auto_generated|ram_block1a14 , main_memory|altsyncram_component|auto_generated|ram_block1a14, super6502, 1
|
||||
instance = comp, \main_memory|altsyncram_component|auto_generated|ram_block1a30 , main_memory|altsyncram_component|auto_generated|ram_block1a30, super6502, 1
|
||||
instance = comp, \main_memory|altsyncram_component|auto_generated|mux2|result_node[6]~13 , main_memory|altsyncram_component|auto_generated|mux2|result_node[6]~13, super6502, 1
|
||||
instance = comp, \cpu_data[7]~input , cpu_data[7]~input, super6502, 1
|
||||
instance = comp, \main_memory|altsyncram_component|auto_generated|ram_block1a7 , main_memory|altsyncram_component|auto_generated|ram_block1a7, super6502, 1
|
||||
instance = comp, \main_memory|altsyncram_component|auto_generated|ram_block1a15 , main_memory|altsyncram_component|auto_generated|ram_block1a15, super6502, 1
|
||||
instance = comp, \main_memory|altsyncram_component|auto_generated|mux2|result_node[7]~14 , main_memory|altsyncram_component|auto_generated|mux2|result_node[7]~14, super6502, 1
|
||||
instance = comp, \main_memory|altsyncram_component|auto_generated|ram_block1a23 , main_memory|altsyncram_component|auto_generated|ram_block1a23, super6502, 1
|
||||
instance = comp, \main_memory|altsyncram_component|auto_generated|ram_block1a31 , main_memory|altsyncram_component|auto_generated|ram_block1a31, super6502, 1
|
||||
instance = comp, \main_memory|altsyncram_component|auto_generated|mux2|result_node[7]~15 , main_memory|altsyncram_component|auto_generated|mux2|result_node[7]~15, super6502, 1
|
||||
instance = comp, \clk_count[1]~1 , clk_count[1]~1, super6502, 1
|
||||
instance = comp, \clk_count[1] , clk_count[1], super6502, 1
|
||||
instance = comp, \clk_count~2 , clk_count~2, super6502, 1
|
||||
instance = comp, \clk_count[2] , clk_count[2], super6502, 1
|
||||
instance = comp, \clk_count~0 , clk_count~0, super6502, 1
|
||||
instance = comp, \clk_count[0] , clk_count[0], super6502, 1
|
||||
instance = comp, \cpu_phi2~0 , cpu_phi2~0, super6502, 1
|
||||
instance = comp, \cpu_phi2~reg0 , cpu_phi2~reg0, super6502, 1
|
||||
instance = comp, \rst~input , rst~input, super6502, 1
|
||||
instance = comp, \cpu_addr[15]~input , cpu_addr[15]~input, super6502, 1
|
||||
instance = comp, \cpu_vpb~input , cpu_vpb~input, super6502, 1
|
||||
instance = comp, \cpu_mlb~input , cpu_mlb~input, super6502, 1
|
||||
instance = comp, \cpu_sync~input , cpu_sync~input, super6502, 1
|
||||
instance = comp, \~QUARTUS_CREATED_UNVM~ , ~QUARTUS_CREATED_UNVM~, super6502, 1
|
||||
instance = comp, \~QUARTUS_CREATED_ADC1~ , ~QUARTUS_CREATED_ADC1~, super6502, 1
|
||||
instance = comp, \~QUARTUS_CREATED_ADC2~ , ~QUARTUS_CREATED_ADC2~, super6502, 1
|
||||
design_name = hard_block
|
||||
instance = comp, \~ALTERA_TMS~~ibuf , ~ALTERA_TMS~~ibuf, hard_block, 1
|
||||
instance = comp, \~ALTERA_TCK~~ibuf , ~ALTERA_TCK~~ibuf, hard_block, 1
|
||||
instance = comp, \~ALTERA_TDI~~ibuf , ~ALTERA_TDI~~ibuf, hard_block, 1
|
||||
instance = comp, \~ALTERA_CONFIG_SEL~~ibuf , ~ALTERA_CONFIG_SEL~~ibuf, hard_block, 1
|
||||
instance = comp, \~ALTERA_nCONFIG~~ibuf , ~ALTERA_nCONFIG~~ibuf, hard_block, 1
|
||||
instance = comp, \~ALTERA_nSTATUS~~ibuf , ~ALTERA_nSTATUS~~ibuf, hard_block, 1
|
||||
instance = comp, \~ALTERA_CONF_DONE~~ibuf , ~ALTERA_CONF_DONE~~ibuf, hard_block, 1
|
||||
@@ -49,3 +49,48 @@ set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
|
||||
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (SystemVerilog)"
|
||||
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
|
||||
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE super6502.sv
|
||||
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
||||
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
|
||||
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
||||
set_location_assignment PIN_V10 -to cpu_led
|
||||
set_location_assignment PIN_W10 -to cpu_vpb
|
||||
set_location_assignment PIN_V9 -to cpu_resb
|
||||
set_location_assignment PIN_W9 -to cpu_rdy
|
||||
set_location_assignment PIN_V8 -to cpu_sob
|
||||
set_location_assignment PIN_V7 -to cpu_phi2
|
||||
set_location_assignment PIN_W6 -to cpu_be
|
||||
set_location_assignment PIN_W5 -to cpu_rwb
|
||||
set_location_assignment PIN_AA14 -to cpu_data[0]
|
||||
set_location_assignment PIN_W12 -to cpu_data[1]
|
||||
set_location_assignment PIN_AB12 -to cpu_data[2]
|
||||
set_location_assignment PIN_AB11 -to cpu_data[3]
|
||||
set_location_assignment PIN_AB10 -to cpu_data[4]
|
||||
set_location_assignment PIN_AA9 -to cpu_data[5]
|
||||
set_location_assignment PIN_AA8 -to cpu_data[6]
|
||||
set_location_assignment PIN_AA7 -to cpu_data[7]
|
||||
set_location_assignment PIN_AA6 -to cpu_addr[15]
|
||||
set_location_assignment PIN_AA5 -to cpu_addr[14]
|
||||
set_location_assignment PIN_AB3 -to cpu_addr[13]
|
||||
set_location_assignment PIN_AB2 -to cpu_addr[12]
|
||||
set_location_assignment PIN_AA2 -to cpu_addr[11]
|
||||
set_location_assignment PIN_Y3 -to cpu_addr[10]
|
||||
set_location_assignment PIN_Y4 -to cpu_addr[9]
|
||||
set_location_assignment PIN_Y5 -to cpu_addr[8]
|
||||
set_location_assignment PIN_Y6 -to cpu_addr[7]
|
||||
set_location_assignment PIN_Y7 -to cpu_addr[6]
|
||||
set_location_assignment PIN_Y8 -to cpu_addr[5]
|
||||
set_location_assignment PIN_AA10 -to cpu_addr[4]
|
||||
set_location_assignment PIN_W11 -to cpu_addr[3]
|
||||
set_location_assignment PIN_Y11 -to cpu_addr[2]
|
||||
set_location_assignment PIN_AB13 -to cpu_addr[1]
|
||||
set_location_assignment PIN_W13 -to cpu_addr[0]
|
||||
set_location_assignment PIN_AA15 -to cpu_sync
|
||||
set_location_assignment PIN_V5 -to cpu_nmib
|
||||
set_location_assignment PIN_W7 -to cpu_mlb
|
||||
set_location_assignment PIN_W8 -to cpu_irqb
|
||||
set_location_assignment PIN_P11 -to clk
|
||||
set_location_assignment PIN_B8 -to rst
|
||||
set_global_assignment -name QIP_FILE ram.qip
|
||||
set_global_assignment -name SDC_FILE super6502.sdc
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
11
hw/fpga/super6502.sdc
Normal file
11
hw/fpga/super6502.sdc
Normal file
@@ -0,0 +1,11 @@
|
||||
#**************************************************************
|
||||
# Create Clock (where ‘clk’ is the user-defined system clock name)
|
||||
#**************************************************************
|
||||
create_clock -name {clk} -period 20ns -waveform {0.000 5.000} [get_ports {clk}]
|
||||
# Constrain the input I/O path
|
||||
set_input_delay -clock {clk} -max 3 [all_inputs]
|
||||
set_input_delay -clock {clk} -min 2 [all_inputs]
|
||||
# Constrain the output I/O path
|
||||
set_output_delay -clock {clk} 2 [all_outputs]
|
||||
|
||||
derive_clock_uncertainty
|
||||
52
hw/fpga/super6502.sv
Normal file
52
hw/fpga/super6502.sv
Normal file
@@ -0,0 +1,52 @@
|
||||
|
||||
module super6502(
|
||||
input clk,
|
||||
input logic rst,
|
||||
|
||||
input logic [15:0] cpu_addr,
|
||||
inout logic [7:0] cpu_data,
|
||||
|
||||
input logic cpu_vpb,
|
||||
input logic cpu_mlb,
|
||||
input logic cpu_rwb,
|
||||
input logic cpu_sync,
|
||||
|
||||
output logic cpu_led,
|
||||
output logic cpu_resb,
|
||||
output logic cpu_rdy,
|
||||
output logic cpu_sob,
|
||||
output logic cpu_irqb,
|
||||
output logic cpu_phi2,
|
||||
output logic cpu_be,
|
||||
output logic cpu_nmib
|
||||
);
|
||||
|
||||
|
||||
logic [7:0] cpu_data_in;
|
||||
assign cpu_data_in = cpu_data;
|
||||
|
||||
logic [7:0] cpu_data_out;
|
||||
assign cpu_data = cpu_rwb ? cpu_data_out : 'z;
|
||||
|
||||
|
||||
logic [2:0] clk_count;
|
||||
always_ff @(posedge clk) begin
|
||||
clk_count <= clk_count + 3'b1;
|
||||
if (clk_count == 3'h4) begin
|
||||
clk_count <= '0;
|
||||
cpu_phi2 <= ~cpu_phi2;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
ram main_memory(
|
||||
.address(cpu_addr[14:0]),
|
||||
.clock(clk),
|
||||
.data(cpu_data_in),
|
||||
.wren(~cpu_rwb),
|
||||
.q(cpu_data_out)
|
||||
);
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
Reference in New Issue
Block a user