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Fix sdram sim

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Just need to add the RTL_SIM define
This commit is contained in:
Byron Lathi
2024-03-03 21:33:28 -08:00
parent 10a72d8e1f
commit aee04b777a
3 changed files with 11 additions and 6 deletions
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3
Makefile
View File

@@ -14,6 +14,9 @@ fpga_image: $(INIT_HEX)
sim: $(INIT_HEX) sim: $(INIT_HEX)
$(MAKE) -C hw/super6502_fpga/src/sim $(MAKE) -C hw/super6502_fpga/src/sim
waves: sim
gtkwave hw/super6502_fpga/src/sim/sim_top.vcd
# SW # SW
.PHONY: toolchain .PHONY: toolchain
toolchain: toolchain:

10
hw/super6502_fpga/ip/sdram_controller/sdram_controller.v
View File

@@ -736,13 +736,13 @@ begin
if (SDR_BWIDTH > AXI_WDATA_WIDTH) if (SDR_BWIDTH > AXI_WDATA_WIDTH)
begin begin
r_addr_1P[0+:BA_WIDTH+ROW_WIDTH+COL_WIDTH-(0-SDR_BWIDTH/AXI_WDATA_WIDTH+1)] <= i_AXI4_AWADDR[BA_WIDTH+ROW_WIDTH+COL_WIDTH-1:0-SDR_BWIDTH/AXI_WDATA_WIDTH+1]; r_addr_1P[0+:BA_WIDTH+ROW_WIDTH+COL_WIDTH-(0-SDR_BWIDTH/AXI_WDATA_WIDTH+1)] <= i_AXI4_AWADDR[BA_WIDTH+ROW_WIDTH+COL_WIDTH-1:0-SDR_BWIDTH/AXI_WDATA_WIDTH+1];
$display("foo_gt\n"); // $display("foo_gt\n");
end end
else if (SDR_BWIDTH == AXI_WDATA_WIDTH) else if (SDR_BWIDTH == AXI_WDATA_WIDTH)
begin begin
r_addr_1P <= {i_AXI4_AWADDR[BA_WIDTH+ROW_WIDTH+COL_WIDTH-1:COL_WIDTH], {(DATA_RATE-1){1'b0}}, i_AXI4_AWADDR[COL_WIDTH-1:DATA_RATE-1]}; r_addr_1P <= {i_AXI4_AWADDR[BA_WIDTH+ROW_WIDTH+COL_WIDTH-1:COL_WIDTH], {(DATA_RATE-1){1'b0}}, i_AXI4_AWADDR[COL_WIDTH-1:DATA_RATE-1]};
//r_addr_1P <= {{(DATA_RATE-1){1'b0}},i_AXI4_AWADDR[BA_WIDTH+ROW_WIDTH+COL_WIDTH-1:DATA_RATE-1]}; //r_addr_1P <= {{(DATA_RATE-1){1'b0}},i_AXI4_AWADDR[BA_WIDTH+ROW_WIDTH+COL_WIDTH-1:DATA_RATE-1]};
$display("foo_eq\n"); // $display("foo_eq\n");
end end
if (SDR_BWIDTH > AXI_WDATA_WIDTH) if (SDR_BWIDTH > AXI_WDATA_WIDTH)
@@ -750,7 +750,7 @@ begin
//r_AXI4_WREADY_c <= 1'b1; //r_AXI4_WREADY_c <= 1'b1;
r_size_1P <= SDR_BWIDTH/AXI_WDATA_WIDTH-1'b1; r_size_1P <= SDR_BWIDTH/AXI_WDATA_WIDTH-1'b1;
r_shift_cnt_1P <= SDR_BWIDTH/AXI_WDATA_WIDTH-1'b1; r_shift_cnt_1P <= SDR_BWIDTH/AXI_WDATA_WIDTH-1'b1;
$display("SDR_BWIDTH %d > AXI_WDATA_WIDTH %d\n", SDR_BWIDTH, AXI_WDATA_WIDTH); // $display("SDR_BWIDTH %d > AXI_WDATA_WIDTH %d\n", SDR_BWIDTH, AXI_WDATA_WIDTH);
end end
else if (SDR_BWIDTH == AXI_WDATA_WIDTH) else if (SDR_BWIDTH == AXI_WDATA_WIDTH)
begin begin
@@ -762,14 +762,14 @@ begin
end end
r_size_1P <= SDR_BWIDTH/AXI_WDATA_WIDTH-1'b1; r_size_1P <= SDR_BWIDTH/AXI_WDATA_WIDTH-1'b1;
r_shift_cnt_1P <= {7{1'b0}}; r_shift_cnt_1P <= {7{1'b0}};
$display("SDR_BWIDTH %d = AXI_WDATA_WIDTH %d\n", SDR_BWIDTH, AXI_WDATA_WIDTH); // $display("SDR_BWIDTH %d = AXI_WDATA_WIDTH %d\n", SDR_BWIDTH, AXI_WDATA_WIDTH);
end end
else else
begin begin
//r_AXI4_WREADY_c <= 1'b1; //r_AXI4_WREADY_c <= 1'b1;
r_size_1P <= AXI_WDATA_WIDTH/SDR_BWIDTH-1'b1; r_size_1P <= AXI_WDATA_WIDTH/SDR_BWIDTH-1'b1;
r_shift_cnt_1P <= AXI_WDATA_WIDTH/SDR_BWIDTH-1'b1; r_shift_cnt_1P <= AXI_WDATA_WIDTH/SDR_BWIDTH-1'b1;
$display("SDR_BWIDTH %d < AXI_WDATA_WIDTH %d\n", SDR_BWIDTH, AXI_WDATA_WIDTH); // $display("SDR_BWIDTH %d < AXI_WDATA_WIDTH %d\n", SDR_BWIDTH, AXI_WDATA_WIDTH);
end end
end end
end end

2
hw/super6502_fpga/src/sim/Makefile
View File

@@ -10,6 +10,8 @@ TB_NAME=sim_top
COPY_FILES=addr_map.mem init_hex.mem COPY_FILES=addr_map.mem init_hex.mem
FLAGS=-DSIM -DRTL_SIM
all: waves all: waves
waves: $(TB_NAME) waves: $(TB_NAME)