Add write and puts tasks to the uart testbench

The write task will transmit a single byte, the puts task will transmit
a string of length n. These do not do any verification, you still have
to look at the output.

hw/fpga/hvl/uart_testbench.sv

@@ -10,15 +10,51 @@ logic [7:0] data_in, data_out;
 logic rw;
 logic RXD, TXD;
 
+logic [7:0] status;
+
 uart dut(.*);
 
 always #1 clk_50 = clk_50 === 1'b0;
+always #100 clk = clk === 1'b0;
+
+task write(logic [7:0] data);
+    @(negedge clk);
+    cs <= '1;
+    addr <= '0;
+    data_in <= data;
+    rw <= '0;
+
+    @(negedge clk);
+    cs <= '0;
+    addr <= '0;
+    data_in <= 8'hxx;
+    rw <= '1;
+
+    do begin
+        @(negedge clk);
+        cs <= '1;
+        addr <= 1'b1;
+        rw <= '1;
+        @(negedge clk);
+    end while (data_out != 8'h0);
+endtask
+
+task puts(string s, int n);
+    for (int i = 0; i < n; i++)
+        write(s[i]);
+endtask
 
 initial begin
     rst <= '1;
-    repeat(5) @(posedge clk_50);
+    repeat(5) @(posedge clk);
     rst <= '0;
-    @(posedge clk_50);
+    rw <= '1;
+    cs <= '0;
+    status <= '0;
+
+    puts("Hello, world!\n", 14);
+
+    $finish();
 end
 
 endmodule

hw/fpga/simulation/modelsim/uart.do

@@ -12,3 +12,6 @@ vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lns
 
 add wave -group {dut} -radix hexadecimal sim:/testbench/dut/*
 
+onfinish stop
+run -all
+