Update network_processor docs, add arp to diagram

hw/super6502_fpga/sources.list

@@ -4,4 +4,5 @@ src/sub/cpu_wrapper/sources.list
 src/sub/network_processor/sources.list
 src/sub/rtl-common/sources.list
 src/sub/sd_controller_wrapper/sources.list
-src/sub/wb2axip/sources.list
+src/sub/wb2axip/sources.list
+src/sub/verilog-ethernet/sources.list

hw/super6502_fpga/src/sub/network_processor/doc/tcp.drawio

@@ -1,6 +1,6 @@
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@@ -99,8 +99,8 @@
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@@ -198,8 +198,8 @@
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@@ -315,11 +315,11 @@
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@@ -377,16 +377,16 @@
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@@ -402,8 +402,8 @@
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@@ -499,7 +499,7 @@
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@@ -531,12 +531,11 @@
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+            <mxPoint x="650" y="170" as="targetPoint" />
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@@ -587,6 +586,37 @@
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+        <mxCell id="1vVpc469gqlHnz9TW-pm-1" value="arp mux/dmux" style="shape=trapezoid;perimeter=trapezoidPerimeter;whiteSpace=wrap;html=1;fixedSize=1;" vertex="1" parent="1">
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     </mxGraphModel>
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hw/super6502_fpga/src/sub/network_processor/src/tcp.sv

@@ -1,28 +1,29 @@
 module tcp #(
-    parameter NUM_TCP=8
+    parameter NUM_TCP=8,
+    parameter DATA_WIDTH=8
 )(
     input i_clk,
     input i_rst,
 
-output  logic           s_reg_axil_awready,
+    output  logic           s_reg_axil_awready,
-input   wire            s_reg_axil_awvalid,
+    input   wire            s_reg_axil_awvalid,
-input   wire [8:0]      s_reg_axil_awaddr,
+    input   wire [8:0]      s_reg_axil_awaddr,
-input   wire [2:0]      s_reg_axil_awprot,
+    input   wire [2:0]      s_reg_axil_awprot,
-output  logic           s_reg_axil_wready,
+    output  logic           s_reg_axil_wready,
-input   wire            s_reg_axil_wvalid,
+    input   wire            s_reg_axil_wvalid,
-input   wire [31:0]     s_reg_axil_wdata,
+    input   wire [31:0]     s_reg_axil_wdata,
-input   wire [3:0]      s_reg_axil_wstrb,
+    input   wire [3:0]      s_reg_axil_wstrb,
-input   wire            s_reg_axil_bready,
+    input   wire            s_reg_axil_bready,
-output  logic           s_reg_axil_bvalid,
+    output  logic           s_reg_axil_bvalid,
-output  logic [1:0]     s_reg_axil_bresp,
+    output  logic [1:0]     s_reg_axil_bresp,
-output  logic           s_reg_axil_arready,
+    output  logic           s_reg_axil_arready,
-input   wire            s_reg_axil_arvalid,
+    input   wire            s_reg_axil_arvalid,
-input   wire [8:0]      s_reg_axil_araddr,
+    input   wire [8:0]      s_reg_axil_araddr,
-input   wire [2:0]      s_reg_axil_arprot,
+    input   wire [2:0]      s_reg_axil_arprot,
-input   wire            s_reg_axil_rready,
+    input   wire            s_reg_axil_rready,
-output  logic           s_reg_axil_rvalid,
+    output  logic           s_reg_axil_rvalid,
-output  logic [31:0]    s_reg_axil_rdata,
+    output  logic [31:0]    s_reg_axil_rdata,
-output  logic [1:0]     s_reg_axil_rresp
+    output  logic [1:0]     s_reg_axil_rresp
 );
 
 tcp_top_regfile_pkg::tcp_top_regfile__in_t tcp_hwif_in;
@@ -57,6 +58,111 @@ tcp_top_regfile u_tcp_top_regfile (
     .hwif_out       (tcp_hwif_out)
 );
 
+localparam KEEP_WIDTH = ((DATA_WIDTH+7)/8);
+localparam USER_WIDTH = 1;
+localparam DEST_WIDTH = 8;
+
+logic [DATA_WIDTH-1:0]          m2s_tx_axis_tdata;
+logic [KEEP_WIDTH-1:0]          m2s_tx_axis_tkeep;
+logic                           m2s_tx_axis_tvalid;
+logic                           m2s_tx_axis_tready;
+logic                           m2s_tx_axis_tlast;
+logic [DEST_WIDTH-1:0]          m2s_tx_axis_tdest;
+logic [USER_WIDTH-1:0]          m2s_tx_axis_tuser;
+
+logic [NUM_TCP*DATA_WIDTH-1:0]  tcp_tx_axis_tdata;
+logic [NUM_TCP*KEEP_WIDTH-1:0]  tcp_tx_axis_tkeep;
+logic [NUM_TCP-1:0]             tcp_tx_axis_tvalid;
+logic [NUM_TCP-1:0]             tcp_tx_axis_tready;
+logic [NUM_TCP-1:0]             tcp_tx_axis_tlast;
+logic [NUM_TCP*DEST_WIDTH-1:0]  tcp_tx_axis_tdest;
+logic [NUM_TCP*USER_WIDTH-1:0]  tcp_tx_axis_tuser;
+
+logic [NUM_TCP*DATA_WIDTH-1:0]  tcp_rx_axis_tdata;
+logic [NUM_TCP*KEEP_WIDTH-1:0]  tcp_rx_axis_tkeep;
+logic [NUM_TCP-1:0]             tcp_rx_axis_tvalid;
+logic [NUM_TCP-1:0]             tcp_rx_axis_tready;
+logic [NUM_TCP-1:0]             tcp_rx_axis_tlast;
+logic [NUM_TCP*DEST_WIDTH-1:0]  tcp_rx_axis_tdest;
+logic [NUM_TCP*USER_WIDTH-1:0]  tcp_rx_axis_tuser;
+
+logic [DATA_WIDTH-1:0]          s2m_rx_axis_tdata;
+logic [KEEP_WIDTH-1:0]          s2m_rx_axis_tkeep;
+logic                           s2m_rx_axis_tvalid;
+logic                           s2m_rx_axis_tready;
+logic                           s2m_rx_axis_tlast;
+logic [DEST_WIDTH-1:0]          s2m_rx_axis_tdest;
+logic [USER_WIDTH-1:0]          s2m_rx_axis_tuser;
+
+
+//m2s dma
+
+//s2m dma
+
+// tx_stream demux
+axis_demux   #(
+    .M_COUNT(NUM_TCP),
+    .DATA_WIDTH(DATA_WIDTH),
+    .M_DEST_WIDTH(DEST_WIDTH),
+    .DEST_ENABLE(1),
+    .TDEST_ROUTE(1)
+) tx_stream_demux (
+    .clk            (i_clk),
+    .rst            (i_rst),
+
+    .s_axis_tdata   (m2s_tx_axis_tdata),
+    .s_axis_tkeep   (m2s_tx_axis_tkeep),
+    .s_axis_tvalid  (m2s_tx_axis_tvalid),
+    .s_axis_tready  (m2s_tx_axis_tready),
+    .s_axis_tlast   (m2s_tx_axis_tlast),
+    .s_axis_tid     ('0),
+    .s_axis_tdest   (m2s_tx_axis_tdest),
+    .s_axis_tuser   (m2s_tx_axis_tuser),
+
+    .m_axis_tdata   (tcp_tx_axis_tdata),
+    .m_axis_tkeep   (tcp_tx_axis_tkeep),
+    .m_axis_tvalid  (tcp_tx_axis_tvalid),
+    .m_axis_tready  (tcp_tx_axis_tready),
+    .m_axis_tlast   (tcp_tx_axis_tlast),
+    .m_axis_tid     (),
+    .m_axis_tdest   (tcp_tx_axis_tdest),
+    .m_axis_tuser   (tcp_tx_axis_tuser),
+
+    .enable         ('1),
+    .drop           ('0),
+    .select         ('0)
+);
+
+// rx_stream arb
+axis_arb_mux #(
+    .S_COUNT(NUM_TCP),
+    .DATA_WIDTH(DATA_WIDTH),
+    .DEST_ENABLE(1),
+    .DEST_WIDTH(8)
+) rx_stream_demux (
+    .clk            (i_clk),
+    .rst            (i_rst),
+
+    .s_axis_tdata   (tcp_rx_axis_tdata),
+    .s_axis_tkeep   (tcp_rx_axis_tkeep),
+    .s_axis_tvalid  (tcp_rx_axis_tvalid),
+    .s_axis_tready  (tcp_rx_axis_tready),
+    .s_axis_tlast   (tcp_rx_axis_tlast),
+    .s_axis_tid     ('0),
+    .s_axis_tdest   (tcp_rx_axis_tdest),
+    .s_axis_tuser   (tcp_rx_axis_tuser),
+
+    .m_axis_tdata   (s2m_rx_axis_tdata),
+    .m_axis_tkeep   (s2m_rx_axis_tkeep),
+    .m_axis_tvalid  (s2m_rx_axis_tvalid),
+    .m_axis_tready  (s2m_rx_axis_tready),
+    .m_axis_tlast   (s2m_rx_axis_tlast),
+    .m_axis_tid     (),
+    .m_axis_tdest   (s2m_rx_axis_tdest),
+    .m_axis_tuser   (s2m_rx_axis_tuser)
+);
+
+
 generate
 
     for (genvar i = 0; i < NUM_TCP; i++) begin
@@ -88,7 +194,23 @@ generate
             .s_cpuif_rd_err         (),
             .s_cpuif_rd_data        (tcp_hwif_in.tcp_streams[i].rd_data),
             .s_cpuif_wr_ack         (tcp_hwif_in.tcp_streams[i].wr_ack),
-            .s_cpuif_wr_err         ()
+            .s_cpuif_wr_err         (),
+
+            .s_axis_tdata           (tcp_tx_axis_tdata[i*DATA_WIDTH+:DATA_WIDTH]),
+            .s_axis_tkeep           (tcp_tx_axis_tkeep[i*KEEP_WIDTH+:KEEP_WIDTH]),
+            .s_axis_tvalid          (tcp_tx_axis_tvalid[i]),
+            .s_axis_tready          (tcp_tx_axis_tready[i]),
+            .s_axis_tlast           (tcp_tx_axis_tlast[i]),
+            .s_axis_tdest           (tcp_tx_axis_tdest[i*DEST_WIDTH+:DEST_WIDTH]),
+            .s_axis_tuser           (tcp_tx_axis_tuser[i*USER_WIDTH+:USER_WIDTH]),
+
+            .m_axis_tdata           (tcp_rx_axis_tdata[i*DATA_WIDTH+:DATA_WIDTH]),
+            .m_axis_tkeep           (tcp_rx_axis_tkeep[i*KEEP_WIDTH+:KEEP_WIDTH]),
+            .m_axis_tvalid          (tcp_rx_axis_tvalid[i]),
+            .m_axis_tready          (tcp_rx_axis_tready[i]),
+            .m_axis_tlast           (tcp_rx_axis_tlast[i]),
+            .m_axis_tdest           (tcp_rx_axis_tdest[i*DEST_WIDTH+:DEST_WIDTH]),
+            .m_axis_tuser           (tcp_rx_axis_tuser[i*USER_WIDTH+:USER_WIDTH])
         );
     end
 endgenerate

hw/super6502_fpga/src/sub/network_processor/src/tcp_stream.sv

@@ -1,4 +1,9 @@
-module tcp_stream(
+module tcp_stream #(
+    parameter DATA_WIDTH = 8,
+    parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
+    parameter DEST_WIDTH = 8,
+    parameter USER_WIDTH = 1
+)(
     input wire clk,
     input wire rst,
 
@@ -13,8 +18,23 @@ module tcp_stream(
     output wire s_cpuif_rd_err,
     output wire [31:0] s_cpuif_rd_data,
     output wire s_cpuif_wr_ack,
-    output wire s_cpuif_wr_err
+    output wire s_cpuif_wr_err,
 
+    input  wire [DATA_WIDTH-1:0]            s_axis_tdata,
+    input  wire [KEEP_WIDTH-1:0]            s_axis_tkeep,
+    input  wire                             s_axis_tvalid,
+    output wire                             s_axis_tready,
+    input  wire                             s_axis_tlast,
+    input  wire [DEST_WIDTH-1:0]            s_axis_tdest,
+    input  wire [USER_WIDTH-1:0]            s_axis_tuser,
+
+    output wire [DATA_WIDTH-1:0]            m_axis_tdata,
+    output wire [KEEP_WIDTH-1:0]            m_axis_tkeep,
+    output wire                             m_axis_tvalid,
+    input  wire                             m_axis_tready,
+    output wire                             m_axis_tlast,
+    output wire [DEST_WIDTH-1:0]            m_axis_tdest,
+    output wire [USER_WIDTH-1:0]            m_axis_tuser
 );
 
 // regs