bslathi19/super6502
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Fix some warnings

Browse Source 
Adds some missing cases, length specifiers.
This commit is contained in:
Byron Lathi
2022-04-11 16:13:38 -05:00
parent 68a422d5e3
commit c9269b2fb8
2 changed files with 11 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

13
hw/fpga/sd_controller.sv
View File

@@ -84,12 +84,12 @@ always_ff @(posedge clk) begin
if (addr < 4'h4) begin
arg[8 * addr +: 8] <= data;
end else if (addr == 4'h4) begin
cmd <= data;
cmd <= data[6:0];
end
end
if (cs & addr == 4'h5 && sd_clk) begin
data_count <= data_count + 1;
data_count <= data_count + 9'b1;
end
if (state.macro == RXCMD) begin
@@ -183,7 +183,7 @@ always_comb begin
if (state.d_bit_count == 8'h0) begin
next_state.count = state.count + 9'b1;
end
next_state.d_bit_count = state.d_bit_count - 8'h1;
next_state.d_bit_count = state.d_bit_count - 3'h1;
end else begin
next_data_flag = '1;
next_state.macro = RXDCRC;
@@ -199,6 +199,11 @@ always_comb begin
next_state.count = '0;
end
end
default: begin
next_state.macro = IDLE;
next_state.count = '0;
end
endcase
end
@@ -220,6 +225,8 @@ always_comb begin
end
RXCMD:;
default:;
endcase
end