bslathi19/super6502
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Merge branch 'no-sram' into 'master'

Browse Source 
Remove fpga RAM

See merge request bslathi19/super6502!9
This commit is contained in:
Byron Lathi
2022-03-21 19:11:20 +00:00
parent c97f2d807a af60d32679
commit ca42bc4915
7 changed files with 5 additions and 204 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
hw/fpga/addr_decode.sv
View File

@@ -1,6 +1,5 @@
module addr_decode( module addr_decode(
input logic [15:0] addr, input logic [15:0] addr,
output logic ram_cs,
output logic sdram_cs, output logic sdram_cs,
output logic rom_cs, output logic rom_cs,
output logic hex_cs, output logic hex_cs,
@@ -10,8 +9,7 @@ module addr_decode(
); );
assign rom_cs = addr >= 16'h8000; assign rom_cs = addr >= 16'h8000;
assign ram_cs = addr < 16'h4000; assign sdram_cs = addr < 16'h7ff0;
assign sdram_cs = addr >= 16'h4000 && addr < 16'h7ff0;
assign hex_cs = addr >= 16'h7ff0 && addr < 16'h7ff4; assign hex_cs = addr >= 16'h7ff0 && addr < 16'h7ff4;
assign uart_cs = addr >= 16'h7ff4 && addr < 16'h7ff6; assign uart_cs = addr >= 16'h7ff4 && addr < 16'h7ff6;
assign board_io_cs = addr == 16'h7ff6; assign board_io_cs = addr == 16'h7ff6;

10
hw/fpga/hvl/cs_testbench.sv
View File

@@ -5,7 +5,6 @@ timeunit 10ns;
timeprecision 1ns; timeprecision 1ns;
logic [15:0] addr; logic [15:0] addr;
logic ram_cs;
logic sdram_cs; logic sdram_cs;
logic rom_cs; logic rom_cs;
logic hex_cs; logic hex_cs;
@@ -13,7 +12,7 @@ logic board_io_cs;
logic uart_cs; logic uart_cs;
logic irq_cs; logic irq_cs;
int cs_count = ram_cs + sdram_cs + rom_cs + hex_cs + uart_cs + board_io_cs; int cs_count = sdram_cs + rom_cs + hex_cs + uart_cs + board_io_cs;
addr_decode dut(.*); addr_decode dut(.*);
@@ -25,12 +24,7 @@ initial begin : TEST_VECTORS
assert(cs_count < 2) assert(cs_count < 2)
else else
$error("Multiple chip selects present!"); $error("Multiple chip selects present!");
if (i < 16'h4000) begin if (i < 16'h7ff0) begin
assert(ram_cs == '1)
else
$error("Bad CS! addr=%4x should have ram_cs!", addr);
end
if (i >= 16'h4000 && i < 16'h7ff0) begin
assert(sdram_cs == '1) assert(sdram_cs == '1)
else else
$error("Bad CS! addr=%4x should have sdram_cs!", addr); $error("Bad CS! addr=%4x should have sdram_cs!", addr);

4
hw/fpga/ram.qip
View File

@@ -1,4 +0,0 @@
set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT"
set_global_assignment -name IP_TOOL_VERSION "18.1"
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "ram.v"]

172
hw/fpga/ram.v
View File

@@ -1,172 +0,0 @@
// megafunction wizard: %RAM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: ram.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 18.1.0 Build 625 09/12/2018 SJ Lite Edition
// ************************************************************
//Copyright (C) 2018 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module ram (
address,
clock,
data,
wren,
q);
input [14:0] address;
input clock;
input [7:0] data;
input wren;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] q = sub_wire0[7:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.intended_device_family = "MAX 10",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 32768,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = 15,
altsyncram_component.width_a = 8,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrData NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "32768"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegData NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "15"
// Retrieval info: PRIVATE: WidthData NUMERIC "8"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32768"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "15"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 15 0 INPUT NODEFVAL "address[14..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
// Retrieval info: CONNECT: @address_a 0 0 15 0 address 0 0 15 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL ram.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf

1
hw/fpga/super6502.qsf
View File

@@ -356,7 +356,6 @@ set_global_assignment -name SYSTEMVERILOG_FILE uart.sv
set_global_assignment -name SYSTEMVERILOG_FILE addr_decode.sv set_global_assignment -name SYSTEMVERILOG_FILE addr_decode.sv
set_global_assignment -name SYSTEMVERILOG_FILE bb_spi_controller.sv set_global_assignment -name SYSTEMVERILOG_FILE bb_spi_controller.sv
set_global_assignment -name SYSTEMVERILOG_FILE super6502.sv set_global_assignment -name SYSTEMVERILOG_FILE super6502.sv
set_global_assignment -name QIP_FILE ram.qip
set_global_assignment -name SDC_FILE super6502.sdc set_global_assignment -name SDC_FILE super6502.sdc
set_global_assignment -name QIP_FILE rom.qip set_global_assignment -name QIP_FILE rom.qip
set_global_assignment -name SYSTEMVERILOG_FILE HexDriver.sv set_global_assignment -name SYSTEMVERILOG_FILE HexDriver.sv

15
hw/fpga/super6502.sv
View File

@@ -56,13 +56,11 @@ assign cpu_data = cpu_rwb ? cpu_data_out : 'z;
logic [7:0] rom_data_out; logic [7:0] rom_data_out;
logic [7:0] ram_data_out;
logic [7:0] sdram_data_out; logic [7:0] sdram_data_out;
logic [7:0] uart_data_out; logic [7:0] uart_data_out;
logic [7:0] irq_data_out; logic [7:0] irq_data_out;
logic [7:0] board_io_data_out; logic [7:0] board_io_data_out;
logic ram_cs;
logic sdram_cs; logic sdram_cs;
logic rom_cs; logic rom_cs;
logic hex_cs; logic hex_cs;
@@ -88,7 +86,6 @@ assign cpu_irqb = irq_data_out == 0;
addr_decode decode( addr_decode decode(
.addr(cpu_addr), .addr(cpu_addr),
.ram_cs(ram_cs),
.sdram_cs(sdram_cs), .sdram_cs(sdram_cs),
.rom_cs(rom_cs), .rom_cs(rom_cs),
.hex_cs(hex_cs), .hex_cs(hex_cs),
@@ -99,9 +96,7 @@ addr_decode decode(
always_comb begin always_comb begin
if (ram_cs) if (sdram_cs)
cpu_data_out = ram_data_out;
else if (sdram_cs)
cpu_data_out = sdram_data_out; cpu_data_out = sdram_data_out;
else if (rom_cs) else if (rom_cs)
cpu_data_out = rom_data_out; cpu_data_out = rom_data_out;
@@ -140,14 +135,6 @@ sdram sdram(
.DRAM_WE_N(DRAM_WE_N) //.we_n .DRAM_WE_N(DRAM_WE_N) //.we_n
); );
ram main_memory(
.address(cpu_addr[14:0]),
.clock(clk),
.data(cpu_data_in),
.wren(~cpu_rwb & ram_cs),
.q(ram_data_out)
);
rom boot_rom( rom boot_rom(
.address(cpu_addr[14:0]), .address(cpu_addr[14:0]),

3
sw/link.ld
View File

@@ -1,8 +1,7 @@
MEMORY MEMORY
{ {
ZP: start = $0, size = $100, type = rw, define = yes; ZP: start = $0, size = $100, type = rw, define = yes;
RAM: start = $0200, size = $3D00, type = rw, define = yes; SDRAM: start = $200, size = $7cf0, type = rw, define = yes;
SDRAM: start = $4000, size = $3ff0, type = rw, define = yes;
ROM: start = $8000, size = $8000, fill = yes, fillval = $ff, file = %O; ROM: start = $8000, size = $8000, fill = yes, fillval = $ff, file = %O;
} }