Fix PLL settings, add cpu output clock

2024-03-03 09:45:04 -08:00
parent 6213d2a227
commit cd1dfa39cb
2 changed files with 8 additions and 8 deletions
--- a/hw/super6502_fpga/src/rtl/super_6502_fpga.sv
+++ b/hw/super6502_fpga/src/rtl/super_6502_fpga.sv
@@ -21,14 +21,14 @@ module super6502_fpga(
    output  logic               o_cpu0_irqb,
    output  logic               o_cpu0_nmib,
    output  logic               o_cpu0_rdy,
-    output  logic               o_cpu0_reset
+    output  logic               o_cpu0_reset,
+    output  logic               o_clk_phi2
 );


 localparam ADDR_WIDTH = 32;
 localparam DATA_WIDTH = 32;

-
 assign pll_cpu_reset = '1;
 assign o_pll_reset = '1;