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Fix PLL settings, add cpu output clock

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This commit is contained in:
Byron Lathi
2024-03-03 09:45:04 -08:00
parent 6213d2a227
commit cd1dfa39cb
2 changed files with 8 additions and 8 deletions
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4
hw/super6502_fpga/src/rtl/super_6502_fpga.sv
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@@ -21,14 +21,14 @@ module super6502_fpga(
output logic o_cpu0_irqb,
output logic o_cpu0_nmib,
output logic o_cpu0_rdy,
output logic o_cpu0_reset
output logic o_cpu0_reset,
output logic o_clk_phi2
);
localparam ADDR_WIDTH = 32;
localparam DATA_WIDTH = 32;
assign pll_cpu_reset = '1;
assign o_pll_reset = '1;

12
hw/super6502_fpga/super6502_fpga.peri.xml
View File

@@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8"?>
<efxpt:design_db name="super6502_fpga" device_def="T20F256" location="/home/byron/Projects/super6502/hw/super6502_fpga" version="2023.1.150" db_version="20231999" last_change_date="Sat Mar 2 22:09:57 2024" xmlns:efxpt="http://www.efinixinc.com/peri_design_db" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/peri_design_db peri_design_db.xsd ">
<efxpt:design_db name="super6502_fpga" device_def="T20F256" location="/home/byron/Projects/super6502/hw/super6502_fpga" version="2023.1.150" db_version="20231999" last_change_date="Sun Mar 3 09:38:42 2024" xmlns:efxpt="http://www.efinixinc.com/peri_design_db" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/peri_design_db peri_design_db.xsd ">
<efxpt:device_info>
<efxpt:iobank_info>
<efxpt:iobank name="1A" iostd="3.3 V LVTTL / LVCMOS"/>
@@ -143,11 +143,11 @@
<efxpt:output_clock name="clk_cpu" number="1" out_divider="100" adv_out_phase_shift="0"/>
<efxpt:adv_prop ref_clock_mode="core" ref_clock1_name="" ext_ref_clock_id="2" clksel_name="" feedback_clock_name="" feedback_mode="internal"/>
</efxpt:pll>
<efxpt:pll name="pll_sdram_clk" pll_def="PLL_BR0" ref_clock_name="" ref_clock_freq="50.0000" multiplier="16" pre_divider="2" post_divider="2" reset_name="o_pll_reset" locked_name="i_pll_locked" is_ipfrz="false" is_bypass_lock="true">
<efxpt:output_clock name="i_sdrclk" number="0" out_divider="4" adv_out_phase_shift="0"/>
<efxpt:output_clock name="i_tACclk" number="1" out_divider="4" adv_out_phase_shift="0"/>
<efxpt:output_clock name="i_sysclk" number="2" out_divider="8" adv_out_phase_shift="0"/>
<efxpt:adv_prop ref_clock_mode="external" ref_clock1_name="" ext_ref_clock_id="3" clksel_name="" feedback_clock_name="i_sdrclk" feedback_mode="core"/>
<efxpt:pll name="pll_sdram_clk" pll_def="PLL_BR0" ref_clock_name="" ref_clock_freq="50.0000" multiplier="8" pre_divider="4" post_divider="2" reset_name="o_pll_reset" locked_name="i_pll_locked" is_ipfrz="false" is_bypass_lock="true">
<efxpt:output_clock name="i_sdrclk" number="0" out_divider="2" adv_out_phase_shift="0"/>
<efxpt:output_clock name="i_tACclk" number="1" out_divider="2" adv_out_phase_shift="0"/>
<efxpt:output_clock name="i_sysclk" number="2" out_divider="4" adv_out_phase_shift="0"/>
<efxpt:adv_prop ref_clock_mode="external" ref_clock1_name="" ext_ref_clock_id="3" clksel_name="" feedback_clock_name="i_sysclk" feedback_mode="core"/>
</efxpt:pll>
</efxpt:pll_info>
<efxpt:lvds_info/>