Make kernel as part of full chip sim

hw/efinix_fpga/simulation/Makefile

@@ -40,6 +40,8 @@ $(TARGET): $(INIT_MEM) $(SRCS)
 	iverilog -g2005-sv $(FLAGS) -s $(TOP_MODULE) -o $(TARGET) $(INC) $(SRCS)
 
 $(INIT_MEM):
+# Make kernel
+	$(MAKE) -C $(REPO_TOP)/sw/kernel
 	$(MAKE) -C $(TEST_FOLDER)
 	cp $(TEST_PROGRAM) ./init_hex.mem
 

sw/bios/Makefile

@@ -2,6 +2,8 @@ CC=../cc65/bin/cl65
 CFLAGS=-T -t none -I. --cpu "65C02" -DRTL_SIM
 LDFLAGS=-C link.ld -m $(NAME).map
 
+FSDIR=$(REPO_TOP)/sw/fsdir
+
 NAME=bios
 
 BIN=$(NAME).bin
@@ -21,9 +23,9 @@ OBJS+=$(patsubst %.c,%.o,$(filter %c,$(SRCS)))
 
 all: $(HEX)
 
-$(HEX): $(BIN)
+$(HEX): $(BIN) $(FSDIR)
 	objcopy --input-target=binary --output-target=verilog $(BIN) $(HEX)
-	cp boot2.bin ../fsdir
+	cp boot2.bin $(FSDIR)
 	cmp $(HEX) $(FPGA_IMG); \
 	RETVAL=$$?; \
     if [ $$RETVAL -eq 0 ]; then \
@@ -34,6 +36,8 @@ $(HEX): $(BIN)
 			echo "Update ROM or rebuild FPGA image!"; \
     fi
 
+$(FSDIR):
+	mkdir $(FSDIR)
 	
 
 $(BIN): $(OBJS)

sw/kernel/Makefile

@@ -7,7 +7,7 @@ NAME=kernel
 
 O65 = $(NAME).o65
 
-FSDIR=../fsdir
+FSDIR=$(REPO_TOP)/sw/fsdir
 
 LISTS=lists
 
@@ -17,9 +17,12 @@ OBJS+=$(patsubst %.s,%.o,$(filter %s,$(SRCS)))
 OBJS+=$(patsubst %.c,%.o,$(filter %c,$(SRCS)))
 
 # Make sure the kernel linked to correct address, no relocation!
-all: $(O65)
+all: $(O65) $(FSDIR)
 	cp $(O65) $(FSDIR)
 
+$(FSDIR):
+	mkdir $(FSDIR)
+
 $(O65): $(OBJS)
 	$(LD) $(CFLAGS) $(LDFLAGS) $(OBJS) -o $@