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First stab at getting sdram working

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This commit is contained in:
Byron Lathi
2022-12-22 20:25:32 -05:00
parent 772f8ff13f
commit cf9aef64ac
14 changed files with 8487 additions and 392 deletions
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100
hw/efinix_fpga/super6502.sv
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@@ -1,27 +1,46 @@
module super6502
(
input [7:0] cpu_data_in,
input cpu_sync,
input cpu_rwb,
input pll_in,
input button_reset,
input pll_cpu_locked,
input clk_50,
input clk_2,
input logic [15:0] cpu_addr,
output logic [7:0] cpu_data_out,
output logic [7:0] cpu_data_oe,
output logic cpu_irqb,
output logic cpu_nmib,
output logic cpu_rdy,
output logic cpu_resb,
output logic pll_cpu_reset,
output logic cpu_phi2,
output logic [7:0] leds
input logic i_sysclk, // Controller Clock (100MHz)
input logic i_sdrclk, // t_su and t_wd clock (200MHz)
input logic i_tACclk, // t_ac clock (200MHz)
input [7:0] cpu_data_in,
input cpu_sync,
input cpu_rwb,
input pll_in,
input button_reset,
input pll_cpu_locked,
input clk_50,
input clk_2,
input logic [15:0] cpu_addr,
output logic [7:0] cpu_data_out,
output logic [7:0] cpu_data_oe,
output logic cpu_irqb,
output logic cpu_nmib,
output logic cpu_rdy,
output logic cpu_resb,
output logic pll_cpu_reset,
output logic cpu_phi2,
output logic [7:0] leds,
output logic o_pll_reset,
output logic o_sdr_CKE,
output logic o_sdr_n_CS,
output logic o_sdr_n_WE,
output logic o_sdr_n_RAS,
output logic o_sdr_n_CAS,
output logic [1:0] o_sdr_BA,
output logic [12:0] o_sdr_ADDR,
input logic [15:0] i_sdr_DATA,
output logic [15:0] o_sdr_DATA,
output logic [15:0] o_sdr_DATA_oe,
output logic [1:0] o_sdr_DQM
);
assign pll_cpu_reset = '1;
assign o_pll_reset = '1;
assign cpu_data_oe = {8{cpu_rwb}};
assign cpu_rdy = '1;
@@ -30,12 +49,14 @@ assign cpu_nmib = '1;
assign cpu_phi2 = clk_2;
logic w_sdr_init_done;
always @(posedge clk_2) begin
if (button_reset == '0) begin
cpu_resb <= '0;
end
else begin
if (cpu_resb == '0) begin
if (cpu_resb == '0 && w_sdr_init_done) begin
cpu_resb <= '1;
end
end
@@ -44,21 +65,26 @@ end
logic w_rom_cs;
logic w_leds_cs;
logic w_sdram_cs;
addr_decode u_addr_decode(
.i_addr(cpu_addr),
.o_rom_cs(w_rom_cs),
.o_leds_cs(w_leds_cs)
.o_leds_cs(w_leds_cs),
.o_sdram_cs(w_sdram_cs)
);
logic [7:0] w_rom_data_out;
logic [7:0] w_leds_data_out;
logic [7:0] w_sdram_data_out;
always_comb begin
if (w_rom_cs)
cpu_data_out = w_rom_data_out;
else if (w_leds_cs)
cpu_data_out= w_leds_data_out;
cpu_data_out = w_leds_data_out;
else if (w_sdram_cs)
cpu_data_out = w_sdram_data_out;
else
cpu_data_out = 'x;
end
@@ -84,4 +110,34 @@ leds u_leds(
.o_leds(leds)
);
sdram_adapter u_sdram_adapter(
.i_cpuclk(clk_2),
.i_arst(~button_reset),
.i_sysclk(i_sysclk),
.i_sdrclk(i_sdrclk),
.i_tACclk(i_tACclk),
.i_cs(w_sdram_cs),
.i_rwb(cpu_rwb),
.i_addr(cpu_addr),
.i_data(cpu_data_in),
.o_data(w_sdram_data_out),
.o_sdr_init_done(w_sdr_init_done),
.o_sdr_CKE(o_sdr_CKE),
.o_sdr_n_CS(o_sdr_n_CS),
.o_sdr_n_RAS(o_sdr_n_RAS),
.o_sdr_n_CAS(o_sdr_n_CAS),
.o_sdr_n_WE(o_sdr_n_WE),
.o_sdr_BA(o_sdr_BA),
.o_sdr_ADDR(o_sdr_ADDR),
.o_sdr_DATA(o_sdr_DATA),
.o_sdr_DATA_oe(o_sdr_DATA_oe),
.i_sdr_DATA(i_sdr_DATA),
.o_sdr_DQM(o_sdr_DQM)
);
endmodule