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Add sd io pins

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This commit is contained in:
Byron Lathi
2024-03-10 16:09:12 -07:00
parent 8f6d074255
commit d3914b3a51
5 changed files with 138 additions and 91 deletions
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14
hw/super6502_fpga/src/rtl/super_6502_fpga.sv
View File

@@ -38,7 +38,13 @@ module super6502_fpga(
output logic o_clk_phi2,
input i_sd_cmd,
output o_sd_cmd
output o_sd_cmd,
output o_sd_cmd_oe,
input i_sd_dat,
output o_sd_dat,
output o_sd_dat_oe,
output o_sd_clk,
output o_sd_cs
);
@@ -69,6 +75,8 @@ assign sdram_ready = |w_sdr_state;
assign master_reset = pre_reset & sdram_ready;
assign o_sd_cs = '1;
logic cpu0_AWVALID;
logic cpu0_AWREADY;
@@ -472,7 +480,9 @@ sd_controller_top u_sd_controller (
.s_apb_pslverr(sd_controller_apb_pslverr),
.i_sd_cmd(i_sd_cmd),
.o_sd_cmd(o_sd_cmd)
.o_sd_cmd(o_sd_cmd),
.o_sd_cmd_oe(o_sd_cmd_oe),
.o_sd_clk(o_sd_clk)
);
endmodule

27
hw/super6502_fpga/src/sim/hvl/sim_top.sv
View File

@@ -59,9 +59,10 @@ logic w_cpu0_rdy;
logic w_cpu0_irqb;
logic w_cpu0_we;
logic w_cpu0_sync;
logic w_clk_phi2;
cpu_65c02 u_cpu0 (
.phi2 (clk_cpu),
.phi2 (w_clk_phi2),
.reset (~w_cpu0_reset),
.AB (w_cpu0_addr),
.RDY (w_cpu0_rdy),
@@ -111,6 +112,18 @@ generate
end
endgenerate
// potential sd card sim here?
logic i_sd_cmd;
logic o_sd_cmd;
logic o_sd_cmd_oe;
logic i_sd_dat;
logic o_sd_dat;
logic i_sd_dat_oe;
logic o_sd_clk;
logic o_sd_cs;
super6502_fpga u_dut (
.i_sysclk (clk_100),
.i_sdrclk (clk_200),
@@ -127,6 +140,7 @@ super6502_fpga u_dut (
.o_cpu0_irqb (w_cpu0_irqb),
.i_cpu0_rwb (~w_cpu0_we),
.i_cpu0_sync (w_cpu0_sync),
.o_clk_phi2 (w_clk_phi2),
.o_sdr_CKE (w_sdr_CKE),
.o_sdr_n_CS (w_sdr_n_CS),
@@ -138,7 +152,16 @@ super6502_fpga u_dut (
.i_sdr_DATA (w_sdr_DQ),
.o_sdr_DATA (w_sdr_DATA),
.o_sdr_DATA_oe (w_sdr_DATA_oe),
.o_sdr_DQM (w_sdr_DQM)
.o_sdr_DQM (w_sdr_DQM),
.i_sd_cmd (i_sd_cmd),
.o_sd_cmd (o_sd_cmd),
.o_sd_cmd_oe (o_sd_cmd_oe),
.i_sd_dat (i_sd_dat),
.o_sd_dat (o_sd_dat),
.o_sd_dat_oe (o_sd_dat_oe),
.o_sd_clk (o_sd_clk),
.o_sd_cs (o_sd_cs)
);

2
hw/super6502_fpga/src/sub/sd_controller

Submodule hw/super6502_fpga/src/sub/sd_controller updated: cb68857a7c...fc2813b809

17
hw/super6502_fpga/super6502_fpga.peri.xml
View File

@@ -282,7 +282,22 @@
<efxpt:gpio name="o_sdr_n_WE" gpio_def="GPIOR_141" mode="output" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:output_config name="o_sdr_n_WE" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
</efxpt:gpio>
<efxpt:gpio name="o_sd_cs" gpio_def="GPIOL_36" mode="output" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:output_config name="o_sd_cs" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="1"/>
</efxpt:gpio>
<efxpt:gpio name="o_sd_clk" gpio_def="GPIOL_26" mode="output" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:output_config name="o_sd_clk" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="1"/>
</efxpt:gpio>
<efxpt:gpio name="io_sd_cmd" gpio_def="GPIOL_25" mode="inout" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:input_config name="i_sd_cmd" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
<efxpt:output_config name="o_sd_cmd" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
<efxpt:output_enable_config name="o_sd_cmd_oe" is_register="false" clock_name="" is_clock_inverted="false"/>
</efxpt:gpio>
<efxpt:gpio name="io_sd_dat" gpio_def="GPIOL_29" mode="inout" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:input_config name="i_sd_dat" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
<efxpt:output_config name="o_sd_dat" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
<efxpt:output_enable_config name="o_sd_dat_oe" is_register="false" clock_name="" is_clock_inverted="false"/>
</efxpt:gpio>
<efxpt:global_unused_config state="input with weak pullup"/>
<efxpt:bus name="cpu_data" mode="inout" msb="7" lsb="0"/>
<efxpt:bus name="cpu_addr" mode="input" msb="15" lsb="0"/>

169
hw/super6502_fpga/super6502_fpga.xml
View File

@@ -1,103 +1,102 @@
<?xml version="1.0" encoding="UTF-8"?>
<efx:project name="super6502_fpga" description="" last_change_date="Sun March 10 2024 12:25:29" location="/home/byron/Projects/super6502/hw/super6502_fpga" sw_version="2023.1.150" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="sync" design_ood="sync" place_ood="sync" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
<efx:project xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" name="super6502_fpga" description="" last_change_date="Sun Mar 10 2024 15:59:47" location="/home/byron/Projects/super6502/hw/super6502_fpga" sw_version="2023.1.150" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="sync" design_ood="sync" place_ood="sync" route_ood="sync" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
<efx:device_info>
<efx:family name="Trion"/>
<efx:device name="T20F256"/>
<efx:timing_model name="I4"/>
<efx:family name="Trion" />
<efx:device name="T20F256" />
<efx:timing_model name="I4" />
</efx:device_info>
<efx:design_info def_veri_version="sv_09" def_vhdl_version="vhdl_2008">
<efx:top_module name="super6502_fpga"/>
<efx:design_file name="src/rtl/super_6502_fpga.sv" version="default" library="default"/>
<efx:design_file name="src/sub/cpu_wrapper/cpu_wrapper.sv" version="default" library="default"/>
<efx:design_file name="src/sub/rtl-common/src/rtl/axi4_lite_rom.sv" version="default" library="default"/>
<efx:design_file name="src/sub/rtl-common/src/rtl/axi4_lite_ram.sv" version="default" library="default"/>
<efx:design_file name="src/sub/rtl-common/src/rtl/ff_cdc.sv" version="default" library="default"/>
<efx:design_file name="src/sub/axi_crossbar/src/rtl/axi_master.sv" version="default" library="default"/>
<efx:design_file name="src/sub/axi_crossbar/src/rtl/axi_slave.sv" version="default" library="default"/>
<efx:design_file name="src/sub/axi_crossbar/src/rtl/slave_addr_decoder.sv" version="default" library="default"/>
<efx:design_file name="src/sub/axi_crossbar/src/rtl/axi_crossbar.sv" version="default" library="default"/>
<efx:design_file name="src/sub/axi_crossbar/src/rtl/rr_scheduler.sv" version="default" library="default"/>
<efx:design_file name="src/sub/rtl-common/src/rtl/axi4_lite_to_apb4.sv" version="default" library="default"/>
<efx:design_file name="src/sub/sd_controller/src/crc16.sv" version="default" library="default"/>
<efx:design_file name="src/sub/sd_controller/src/crc7.sv" version="default" library="default"/>
<efx:design_file name="src/sub/sd_controller/src/sd_control.sv" version="default" library="default"/>
<efx:design_file name="src/sub/sd_controller/src/sd_controller_top.sv" version="default" library="default"/>
<efx:design_file name="src/sub/sd_controller/src/sd_command.sv" version="default" library="default"/>
<efx:design_file name="src/sub/sd_controller/src/regs/sd_controller_regs.sv" version="default" library="default"/>
<efx:design_file name="src/sub/sd_controller/src/regs/sd_controller_regs_pkg.sv" version="default" library="default"/>
<efx:top_vhdl_arch name=""/>
<efx:top_module name="super6502_fpga" />
<efx:design_file name="src/rtl/super_6502_fpga.sv" version="default" library="default" />
<efx:design_file name="src/sub/cpu_wrapper/cpu_wrapper.sv" version="default" library="default" />
<efx:design_file name="src/sub/rtl-common/src/rtl/axi4_lite_rom.sv" version="default" library="default" />
<efx:design_file name="src/sub/rtl-common/src/rtl/axi4_lite_ram.sv" version="default" library="default" />
<efx:design_file name="src/sub/rtl-common/src/rtl/ff_cdc.sv" version="default" library="default" />
<efx:design_file name="src/sub/axi_crossbar/src/rtl/axi_master.sv" version="default" library="default" />
<efx:design_file name="src/sub/axi_crossbar/src/rtl/axi_slave.sv" version="default" library="default" />
<efx:design_file name="src/sub/axi_crossbar/src/rtl/slave_addr_decoder.sv" version="default" library="default" />
<efx:design_file name="src/sub/axi_crossbar/src/rtl/axi_crossbar.sv" version="default" library="default" />
<efx:design_file name="src/sub/axi_crossbar/src/rtl/rr_scheduler.sv" version="default" library="default" />
<efx:design_file name="src/sub/rtl-common/src/rtl/axi4_lite_to_apb4.sv" version="default" library="default" />
<efx:design_file name="src/sub/sd_controller/src/crc16.sv" version="default" library="default" />
<efx:design_file name="src/sub/sd_controller/src/crc7.sv" version="default" library="default" />
<efx:design_file name="src/sub/sd_controller/src/sd_control.sv" version="default" library="default" />
<efx:design_file name="src/sub/sd_controller/src/sd_controller_top.sv" version="default" library="default" />
<efx:design_file name="src/sub/sd_controller/src/sd_command.sv" version="default" library="default" />
<efx:design_file name="src/sub/sd_controller/src/regs/sd_controller_regs.sv" version="default" library="default" />
<efx:design_file name="src/sub/sd_controller/src/regs/sd_controller_regs_pkg.sv" version="default" library="default" />
<efx:top_vhdl_arch name="" />
</efx:design_info>
<efx:constraint_info>
<efx:sdc_file name="constraints/constraints.sdc"/>
<efx:inter_file name=""/>
<efx:sdc_file name="constraints/constraints.sdc" />
<efx:inter_file name="" />
</efx:constraint_info>
<efx:sim_info/>
<efx:misc_info/>
<efx:sim_info />
<efx:misc_info />
<efx:ip_info>
<efx:ip instance_name="sdram_controller" path="ip/sdram_controller/settings.json">
<efx:ip_src_file name="sdram_controller.v"/>
<efx:ip_src_file name="sdram_controller.v" />
</efx:ip>
</efx:ip_info>
<efx:synthesis tool_name="efx_map">
<efx:param name="work_dir" value="work_syn" value_type="e_string"/>
<efx:param name="write_efx_verilog" value="on" value_type="e_bool"/>
<efx:param name="allow-const-ram-index" value="0" value_type="e_option"/>
<efx:param name="blackbox-error" value="1" value_type="e_option"/>
<efx:param name="blast_const_operand_adders" value="1" value_type="e_option"/>
<efx:param name="bram_output_regs_packing" value="1" value_type="e_option"/>
<efx:param name="create-onehot-fsms" value="0" value_type="e_option"/>
<efx:param name="fanout-limit" value="0" value_type="e_integer"/>
<efx:param name="hdl-compile-unit" value="1" value_type="e_option"/>
<efx:param name="infer-clk-enable" value="3" value_type="e_option"/>
<efx:param name="infer-sync-set-reset" value="1" value_type="e_option"/>
<efx:param name="max_ram" value="-1" value_type="e_integer"/>
<efx:param name="max_mult" value="-1" value_type="e_integer"/>
<efx:param name="min-sr-fanout" value="0" value_type="e_integer"/>
<efx:param name="min-ce-fanout" value="0" value_type="e_integer"/>
<efx:param name="mult-decomp-retime" value="0" value_type="e_option"/>
<efx:param name="mode" value="speed" value_type="e_option"/>
<efx:param name="operator-sharing" value="0" value_type="e_option"/>
<efx:param name="optimize-adder-tree" value="0" value_type="e_option"/>
<efx:param name="optimize-zero-init-rom" value="1" value_type="e_option"/>
<efx:param name="retiming" value="1" value_type="e_option"/>
<efx:param name="seq_opt" value="1" value_type="e_option"/>
<efx:param name="seq-opt-sync-only" value="0" value_type="e_option"/>
<efx:param name="mult_input_regs_packing" value="1" value_type="e_option"/>
<efx:param name="mult_output_regs_packing" value="1" value_type="e_option"/>
<efx:param name="include" value="ip/sdram_controller" value_type="e_string"/>
<efx:param name="work_dir" value="work_syn" value_type="e_string" />
<efx:param name="write_efx_verilog" value="on" value_type="e_bool" />
<efx:param name="allow-const-ram-index" value="0" value_type="e_option" />
<efx:param name="blackbox-error" value="1" value_type="e_option" />
<efx:param name="blast_const_operand_adders" value="1" value_type="e_option" />
<efx:param name="bram_output_regs_packing" value="1" value_type="e_option" />
<efx:param name="create-onehot-fsms" value="0" value_type="e_option" />
<efx:param name="fanout-limit" value="0" value_type="e_integer" />
<efx:param name="hdl-compile-unit" value="1" value_type="e_option" />
<efx:param name="infer-clk-enable" value="3" value_type="e_option" />
<efx:param name="infer-sync-set-reset" value="1" value_type="e_option" />
<efx:param name="max_ram" value="-1" value_type="e_integer" />
<efx:param name="max_mult" value="-1" value_type="e_integer" />
<efx:param name="min-sr-fanout" value="0" value_type="e_integer" />
<efx:param name="min-ce-fanout" value="0" value_type="e_integer" />
<efx:param name="mult-decomp-retime" value="0" value_type="e_option" />
<efx:param name="mode" value="speed" value_type="e_option" />
<efx:param name="operator-sharing" value="0" value_type="e_option" />
<efx:param name="optimize-adder-tree" value="0" value_type="e_option" />
<efx:param name="optimize-zero-init-rom" value="1" value_type="e_option" />
<efx:param name="retiming" value="1" value_type="e_option" />
<efx:param name="seq_opt" value="1" value_type="e_option" />
<efx:param name="seq-opt-sync-only" value="0" value_type="e_option" />
<efx:param name="mult_input_regs_packing" value="1" value_type="e_option" />
<efx:param name="mult_output_regs_packing" value="1" value_type="e_option" />
<efx:param name="include" value="ip/sdram_controller" value_type="e_string" />
</efx:synthesis>
<efx:place_and_route tool_name="efx_pnr">
<efx:param name="work_dir" value="work_pnr" value_type="e_string"/>
<efx:param name="verbose" value="off" value_type="e_bool"/>
<efx:param name="load_delaym" value="on" value_type="e_bool"/>
<efx:param name="optimization_level" value="NULL" value_type="e_option"/>
<efx:param name="seed" value="1" value_type="e_integer"/>
<efx:param name="placer_effort_level" value="2" value_type="e_option"/>
<efx:param name="max_threads" value="-1" value_type="e_integer"/>
<efx:param name="work_dir" value="work_pnr" value_type="e_string" />
<efx:param name="verbose" value="off" value_type="e_bool" />
<efx:param name="load_delaym" value="on" value_type="e_bool" />
<efx:param name="optimization_level" value="NULL" value_type="e_option" />
<efx:param name="seed" value="1" value_type="e_integer" />
<efx:param name="placer_effort_level" value="2" value_type="e_option" />
<efx:param name="max_threads" value="-1" value_type="e_integer" />
</efx:place_and_route>
<efx:bitstream_generation tool_name="efx_pgm">
<efx:param name="mode" value="active" value_type="e_option"/>
<efx:param name="width" value="1" value_type="e_option"/>
<efx:param name="enable_roms" value="smart" value_type="e_option"/>
<efx:param name="spi_low_power_mode" value="on" value_type="e_bool"/>
<efx:param name="io_weak_pullup" value="on" value_type="e_bool"/>
<efx:param name="oscillator_clock_divider" value="DIV8" value_type="e_option"/>
<efx:param name="bitstream_compression" value="off" value_type="e_bool"/>
<efx:param name="enable_external_master_clock" value="off" value_type="e_bool"/>
<efx:param name="active_capture_clk_edge" value="posedge" value_type="e_option"/>
<efx:param name="jtag_usercode" value="0xFFFFFFFF" value_type="e_string"/>
<efx:param name="release_tri_then_reset" value="on" value_type="e_bool"/>
<efx:param name="four_byte_addressing" value="off" value_type="e_bool"/>
<efx:param name="generate_bit" value="on" value_type="e_bool"/>
<efx:param name="generate_bitbin" value="off" value_type="e_bool"/>
<efx:param name="generate_hex" value="on" value_type="e_bool"/>
<efx:param name="generate_hexbin" value="off" value_type="e_bool"/>
<efx:param name="cold_boot" value="off" value_type="e_bool"/>
<efx:param name="cascade" value="off" value_type="e_option"/>
<efx:param name="mode" value="active" value_type="e_option" />
<efx:param name="width" value="1" value_type="e_option" />
<efx:param name="enable_roms" value="smart" value_type="e_option" />
<efx:param name="spi_low_power_mode" value="on" value_type="e_bool" />
<efx:param name="io_weak_pullup" value="on" value_type="e_bool" />
<efx:param name="oscillator_clock_divider" value="DIV8" value_type="e_option" />
<efx:param name="bitstream_compression" value="off" value_type="e_bool" />
<efx:param name="enable_external_master_clock" value="off" value_type="e_bool" />
<efx:param name="active_capture_clk_edge" value="posedge" value_type="e_option" />
<efx:param name="jtag_usercode" value="0xFFFFFFFF" value_type="e_string" />
<efx:param name="release_tri_then_reset" value="on" value_type="e_bool" />
<efx:param name="four_byte_addressing" value="off" value_type="e_bool" />
<efx:param name="generate_bit" value="on" value_type="e_bool" />
<efx:param name="generate_bitbin" value="off" value_type="e_bool" />
<efx:param name="generate_hex" value="on" value_type="e_bool" />
<efx:param name="generate_hexbin" value="off" value_type="e_bool" />
<efx:param name="cold_boot" value="off" value_type="e_bool" />
<efx:param name="cascade" value="off" value_type="e_option" />
</efx:bitstream_generation>
<efx:debugger>
<efx:param name="work_dir" value="work_dbg" value_type="e_string"/>
<efx:param name="auto_instantiation" value="off" value_type="e_bool"/>
<efx:param name="profile" value="NONE" value_type="e_string"/>
<efx:param name="work_dir" value="work_dbg" value_type="e_string" />
<efx:param name="auto_instantiation" value="off" value_type="e_bool" />
<efx:param name="profile" value="NONE" value_type="e_string" />
</efx:debugger>
</efx:project>
</efx:project>