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Add sd io pins

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This commit is contained in:
Byron Lathi
2024-03-10 16:09:12 -07:00
parent 8f6d074255
commit d3914b3a51
5 changed files with 138 additions and 91 deletions
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14
hw/super6502_fpga/src/rtl/super_6502_fpga.sv
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@@ -38,7 +38,13 @@ module super6502_fpga(
output logic o_clk_phi2,
input i_sd_cmd,
output o_sd_cmd
output o_sd_cmd,
output o_sd_cmd_oe,
input i_sd_dat,
output o_sd_dat,
output o_sd_dat_oe,
output o_sd_clk,
output o_sd_cs
);
@@ -69,6 +75,8 @@ assign sdram_ready = |w_sdr_state;
assign master_reset = pre_reset & sdram_ready;
assign o_sd_cs = '1;
logic cpu0_AWVALID;
logic cpu0_AWREADY;
@@ -472,7 +480,9 @@ sd_controller_top u_sd_controller (
.s_apb_pslverr(sd_controller_apb_pslverr),
.i_sd_cmd(i_sd_cmd),
.o_sd_cmd(o_sd_cmd)
.o_sd_cmd(o_sd_cmd),
.o_sd_cmd_oe(o_sd_cmd_oe),
.o_sd_clk(o_sd_clk)
);
endmodule

27
hw/super6502_fpga/src/sim/hvl/sim_top.sv
View File

@@ -59,9 +59,10 @@ logic w_cpu0_rdy;
logic w_cpu0_irqb;
logic w_cpu0_we;
logic w_cpu0_sync;
logic w_clk_phi2;
cpu_65c02 u_cpu0 (
.phi2 (clk_cpu),
.phi2 (w_clk_phi2),
.reset (~w_cpu0_reset),
.AB (w_cpu0_addr),
.RDY (w_cpu0_rdy),
@@ -111,6 +112,18 @@ generate
end
endgenerate
// potential sd card sim here?
logic i_sd_cmd;
logic o_sd_cmd;
logic o_sd_cmd_oe;
logic i_sd_dat;
logic o_sd_dat;
logic i_sd_dat_oe;
logic o_sd_clk;
logic o_sd_cs;
super6502_fpga u_dut (
.i_sysclk (clk_100),
.i_sdrclk (clk_200),
@@ -127,6 +140,7 @@ super6502_fpga u_dut (
.o_cpu0_irqb (w_cpu0_irqb),
.i_cpu0_rwb (~w_cpu0_we),
.i_cpu0_sync (w_cpu0_sync),
.o_clk_phi2 (w_clk_phi2),
.o_sdr_CKE (w_sdr_CKE),
.o_sdr_n_CS (w_sdr_n_CS),
@@ -138,7 +152,16 @@ super6502_fpga u_dut (
.i_sdr_DATA (w_sdr_DQ),
.o_sdr_DATA (w_sdr_DATA),
.o_sdr_DATA_oe (w_sdr_DATA_oe),
.o_sdr_DQM (w_sdr_DQM)
.o_sdr_DQM (w_sdr_DQM),
.i_sd_cmd (i_sd_cmd),
.o_sd_cmd (o_sd_cmd),
.o_sd_cmd_oe (o_sd_cmd_oe),
.i_sd_dat (i_sd_dat),
.o_sd_dat (o_sd_dat),
.o_sd_dat_oe (o_sd_dat_oe),
.o_sd_clk (o_sd_clk),
.o_sd_cs (o_sd_cs)
);

2
hw/super6502_fpga/src/sub/sd_controller

Submodule hw/super6502_fpga/src/sub/sd_controller updated: cb68857a7c...fc2813b809

17
hw/super6502_fpga/super6502_fpga.peri.xml
View File

@@ -282,7 +282,22 @@
<efxpt:gpio name="o_sdr_n_WE" gpio_def="GPIOR_141" mode="output" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:output_config name="o_sdr_n_WE" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
</efxpt:gpio>
<efxpt:gpio name="o_sd_cs" gpio_def="GPIOL_36" mode="output" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:output_config name="o_sd_cs" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="1"/>
</efxpt:gpio>
<efxpt:gpio name="o_sd_clk" gpio_def="GPIOL_26" mode="output" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:output_config name="o_sd_clk" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="1"/>
</efxpt:gpio>
<efxpt:gpio name="io_sd_cmd" gpio_def="GPIOL_25" mode="inout" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:input_config name="i_sd_cmd" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
<efxpt:output_config name="o_sd_cmd" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
<efxpt:output_enable_config name="o_sd_cmd_oe" is_register="false" clock_name="" is_clock_inverted="false"/>
</efxpt:gpio>
<efxpt:gpio name="io_sd_dat" gpio_def="GPIOL_29" mode="inout" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:input_config name="i_sd_dat" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
<efxpt:output_config name="o_sd_dat" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
<efxpt:output_enable_config name="o_sd_dat_oe" is_register="false" clock_name="" is_clock_inverted="false"/>
</efxpt:gpio>
<efxpt:global_unused_config state="input with weak pullup"/>
<efxpt:bus name="cpu_data" mode="inout" msb="7" lsb="0"/>
<efxpt:bus name="cpu_addr" mode="input" msb="15" lsb="0"/>

3
hw/super6502_fpga/super6502_fpga.xml
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@@ -1,5 +1,4 @@
<?xml version="1.0" encoding="UTF-8"?>
<efx:project name="super6502_fpga" description="" last_change_date="Sun March 10 2024 12:25:29" location="/home/byron/Projects/super6502/hw/super6502_fpga" sw_version="2023.1.150" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="sync" design_ood="sync" place_ood="sync" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
<efx:project xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" name="super6502_fpga" description="" last_change_date="Sun Mar 10 2024 15:59:47" location="/home/byron/Projects/super6502/hw/super6502_fpga" sw_version="2023.1.150" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="sync" design_ood="sync" place_ood="sync" route_ood="sync" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
<efx:device_info>
<efx:family name="Trion" />
<efx:device name="T20F256" />