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Add read flag to sd controller

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Read flag is set when the sd controller reads response data in from the
sd card. When the cpu reads from the controller, the flag is reset.

This flag does not trigger an interrupt, it mmust be polled.
This commit is contained in:
Byron Lathi
2022-04-10 23:16:10 -05:00
parent 385efb2511
commit f5f1d7ccc6
2 changed files with 54 additions and 17 deletions
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34
hw/fpga/sd_controller.sv
View File

@@ -12,13 +12,30 @@ module sd_controller(
output logic o_sd_cmd,
input i_sd_data,
output logic o_sd_data
output logic o_sd_data,
output logic [7:0] data_out
);
logic [31:0] arg;
logic [5:0] cmd;
logic [47:0] rxcmd_buf;
logic [31:0] rx_val;
assign rx_val = rxcmd_buf[39:8];
always_comb begin
data_out = 'x;
if (addr < 4'h4) begin
data_out = rx_val[8 * addr +: 8];
end else if (addr == 4'h4) begin
data_out = read_flag;
end
end
logic read_flag, next_read_flag;
typedef enum bit [2:0] {IDLE, LOAD, CRC, TXCMD, RXCMD} macro_t;
struct packed {
@@ -30,16 +47,25 @@ always_ff @(posedge clk) begin
if (rst) begin
state.macro <= IDLE;
state.count <= '0;
read_flag <= '0;
end else begin
if (state.macro == TXCMD || state.macro == CRC) begin
if (sd_clk) begin
state <= next_state;
end
end else if (state.macro == RXCMD) begin
if (~sd_clk) begin
state <= next_state;
end
end else begin
state <= next_state;
end
end
if (sd_clk) begin
read_flag <= next_read_flag;
end
if (cs & ~rw) begin
if (addr < 4'h4) begin
arg[8 * addr +: 8] <= data;
@@ -71,6 +97,7 @@ crc7 u_crc7(
always_comb begin
next_state = state;
next_read_flag = read_flag;
case (state.macro)
IDLE: begin
@@ -81,6 +108,10 @@ always_comb begin
if (addr == 4'h4 & cs & ~rw) begin // transmit if cpu writes to cmd
next_state.macro = LOAD;
end
if (addr == 4'h4 & cs & rw) begin
next_read_flag = '0;
end
end
LOAD: begin
@@ -104,6 +135,7 @@ always_comb begin
if (state.count < 47) begin
next_state.count = state.count + 6'b1;
end else begin
next_read_flag = '1;
next_state.macro = IDLE;
next_state.count = '0;
end

37
hw/fpga/super6502.sv
View File

@@ -73,6 +73,7 @@ logic [7:0] uart_data_out;
logic [7:0] irq_data_out;
logic [7:0] board_io_data_out;
logic [7:0] mm_data_out;
logic [7:0] sd_data_out;
logic sdram_cs;
logic rom_cs;
@@ -85,8 +86,8 @@ logic mm_cs2;
logic sd_cs;
cpu_clk cpu_clk(
.inclk0(clk_50),
.c0(clk)
.inclk0(clk_50),
.c0(clk)
);
always @(posedge clk) begin
@@ -106,16 +107,16 @@ logic [23:0] mm_addr;
assign mm_addr = {mm_MO, cpu_addr[11:0]};
memory_mapper memory_mapper(
.clk(clk),
.clk(clk),
.rst(rst),
.rw(cpu_rwb),
.cs(mm_cs1),
.MM_cs(mm_cs2),
.RS(cpu_addr[3:0]),
.MA(cpu_addr[15:12]),
.data_in(cpu_data_in),
.data_out(mm_data_out),
.MO(mm_MO)
.rw(cpu_rwb),
.cs(mm_cs1),
.MM_cs(mm_cs2),
.RS(cpu_addr[3:0]),
.MA(cpu_addr[15:12]),
.data_in(cpu_data_in),
.data_out(mm_data_out),
.MO(mm_MO)
);
addr_decode decode(
@@ -126,8 +127,8 @@ addr_decode decode(
.uart_cs(uart_cs),
.irq_cs(irq_cs),
.board_io_cs(board_io_cs),
.mm_cs1(mm_cs1),
.mm_cs2(mm_cs2),
.mm_cs1(mm_cs1),
.mm_cs2(mm_cs2),
.sd_cs(sd_cs)
);
@@ -143,8 +144,10 @@ always_comb begin
cpu_data_out = irq_data_out;
else if (board_io_cs)
cpu_data_out = board_io_data_out;
else if (mm_cs1)
cpu_data_out = mm_data_out;
else if (mm_cs1)
cpu_data_out = mm_data_out;
else if (sd_cs)
cpu_data_out = sd_data_out;
else
cpu_data_out = 'x;
end
@@ -231,7 +234,9 @@ sd_controller sd_controller(
.o_sd_cmd(o_sd_cmd),
.i_sd_data(i_sd_data),
.o_sd_data(o_sd_data)
.o_sd_data(o_sd_data),
.data_out(sd_data_out)
);
always_ff @(posedge clk_50) begin