Commit Graph

6 Commits

Author SHA1 Message Date
Byron Lathi
59d2d4f601 Add receive logic to UART
The UART has a receive buffer which will fill up when it receives bytes.
Once the buffer is full, it raises the RX flag until the value is read
by the cpu.
2022-03-14 16:41:59 -05:00
Byron Lathi
ed18b381f3 Change "clkdiv" to "tx_clkdiv" 2022-03-14 15:22:18 -05:00
Byron Lathi
264263b0d9 Change "state" to "tx_state" etc. 2022-03-14 15:10:59 -05:00
Byron Lathi
b2344d986e Add UART interrupts
Currently an interrupt is triggered any time there is any activity on
the UART_RXD line, but later it will only trigger once there is data
ready to be read.
2022-03-14 14:57:45 -05:00
Byron Lathi
f8da9206d9 Refactor uart.sv to better allow cpu control
Added new signal tx_flag, which indicates whether the transmitter is
ready for new data.

Added status register, which when read will return the tx_flag bit, as
well as others that can be implemented.

Added new state IDLE, which resets the TX flag and allows new data to be
written.

Added code to allow for different baud rates, though it is still fixed
currently.
2022-03-14 00:00:55 -05:00
Byron Lathi
e063e9f6a3 Add basic UART device
So far the device only transmits the ASCII set on repeat, but will
become fully featured later.
2022-03-13 19:42:41 -05:00