e063e9f6a3
So far the device only transmits the ASCII set on repeat, but will become fully featured later.
110 lines
2.1 KiB
Systemverilog
110 lines
2.1 KiB
Systemverilog
module uart(
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input clk_50,
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input clk,
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input rst,
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input cs,
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input rw,
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input [7:0] data_in,
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input [1:0] addr,
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input RXD,
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output logic TXD,
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output logic [7:0] data_out
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);
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//Handle reading and writing registers
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logic [7:0] _data [3:0];
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assign data_out = _data[addr];
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always_ff @(posedge clk) begin
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if (rst)
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_data = '{default:'0};
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if (~rw & cs)
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_data[addr] <= data_in;
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end
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// state controller
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typedef enum bit [1:0] {START, DATA, PARITY, STOP} macro_t;
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struct packed {
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macro_t macro;
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logic [3:0] count;
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} state, next_state;
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localparam logic [3:0] maxcount = 4'h7;
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logic [7:0] testval, next_testval;
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// baud rate: 9600
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logic [14:0] clkdiv;
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always_ff @(posedge clk_50) begin
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if (rst) begin
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clkdiv <= 0;
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state.macro <= STOP;
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state.count <= 3'b0;
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testval <= '0;
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end else begin
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if (clkdiv == 5207) begin
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clkdiv <= 0;
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state <= next_state;
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testval <= next_testval;
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end else begin
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clkdiv <= clkdiv + 15'b1;
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end
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end
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end
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always_comb begin
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next_state = state;
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unique case (state.macro)
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START: begin
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next_state.macro = DATA;
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next_state.count = 3'b0;
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end
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DATA: begin
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if (state.count == maxcount) begin
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next_state.macro = STOP; // or PARITY
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next_state.count = 3'b0;
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end else begin
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next_state.count = state.count + 3'b1;
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next_state.macro = DATA;
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end
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end
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PARITY: begin
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end
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STOP: begin
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next_state.macro = START;
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next_state.count = '0;
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end
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endcase
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end
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always_comb begin
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TXD = '1;
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next_testval = testval;
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unique case (state.macro)
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START: begin
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TXD = '0;
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end
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DATA: begin
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TXD = testval[state.count];
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end
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PARITY: begin
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end
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STOP: begin
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next_testval = testval + 8'b1;
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TXD = '1;
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end
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endcase
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end
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endmodule
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