Byron Lathi e063e9f6a3 Add basic UART device ...

So far the device only transmits the ASCII set on repeat, but will
become fully featured later.

2022-03-13 19:42:41 -05:00

hw

Add basic UART device

2022-03-13 19:42:41 -05:00

sw

Update Makefile

2022-03-12 22:40:48 -06:00

.gitlab-ci.yml

Update .gitlab-ci.yml

2022-03-10 22:27:43 +00:00

Description

No description provided

5.5 MiB

Languages

SystemVerilog 47.7%

Verilog 41.8%

Python 4.8%

VHDL 2%

Assembly 2%

Other 1.6%