Byron Lathi
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79675ec773
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Clean up modelsim folder
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2022-03-12 19:41:08 -06:00 |
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Byron Lathi
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28836259e2
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Don't track vcd files either
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2022-03-12 19:34:43 -06:00 |
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Byron Lathi
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b7c92d3117
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Don't track signaltap
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2022-03-12 19:30:37 -06:00 |
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Byron Lathi
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ca4288df66
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Change addr_decode test to use new io locations
Instead of whatever was there before, the new io locations are ram, rom,
and the hex digits.
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2022-03-12 19:25:34 -06:00 |
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Byron Lathi
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3d9d340520
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Get the FPGA part working
This changes some of the clocks, fixes a bug in the seven segment stuff.
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2022-03-11 22:55:26 -06:00 |
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Byron Lathi
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cdf3da9b13
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Add hex drivers
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2022-03-11 18:25:55 -06:00 |
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Byron Lathi
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ad55f986f5
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Add bb_spi_controller
Bit banged spi controller, very simple but very slow.
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2022-03-08 15:26:01 -06:00 |
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Byron Lathi
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e1f50e825d
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Ignore gerber output files and folders
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2022-03-08 15:25:05 -06:00 |
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Byron Lathi
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de320babfc
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Fix ground plane not connected
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2022-03-08 15:23:20 -06:00 |
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Byron Lathi
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16b50dcca7
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Add io chip select
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2022-03-05 23:15:50 -06:00 |
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Byron Lathi
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c70272f9de
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Add addr_decode and testbench
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2022-03-05 20:11:47 -06:00 |
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Byron Lathi
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37e122197f
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Refactor CI into one file
Remove the downstream stuff and consolidate the hw and sw pipelines into
one.
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2022-03-05 19:22:00 -06:00 |
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Byron Lathi
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8855bedaf2
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Change to directory before running quartus
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2022-03-05 19:11:53 -06:00 |
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Byron Lathi
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e29bf45ecb
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Add fpga ci
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2022-03-05 19:00:06 -06:00 |
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Byron Lathi
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bc98b67ddf
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Add boot rom
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2022-03-05 18:12:27 -06:00 |
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Byron Lathi
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a096f09fc9
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Remove board backups folder
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2022-03-05 17:52:51 -06:00 |
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Byron Lathi
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aca17a9cf8
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Create quartus project
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2022-03-05 17:52:42 -06:00 |
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Byron Lathi
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b996d93c99
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Create quartus project
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2022-03-05 16:38:12 -06:00 |
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Byron Lathi
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d364c216b8
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Create board
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2022-03-05 16:25:20 -06:00 |
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Byron Lathi
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f0b1ec65c3
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Create project
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2022-03-05 12:50:54 -06:00 |
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