Byron Lathi
c7e8cc3798
Implement enable byte in hw
2022-03-12 21:45:30 -06:00
Byron Lathi
627b6a746a
Add high pair of seven segment displays
...
This also increases the number of registers to 4, one more for the high
pair of displays, and a final one for a mask register which has not been
implemented yet.
2022-03-12 21:24:37 -06:00
Byron Lathi
79675ec773
Clean up modelsim folder
2022-03-12 19:41:08 -06:00
Byron Lathi
28836259e2
Don't track vcd files either
2022-03-12 19:34:43 -06:00
Byron Lathi
b7c92d3117
Don't track signaltap
2022-03-12 19:30:37 -06:00
Byron Lathi
ca4288df66
Change addr_decode test to use new io locations
...
Instead of whatever was there before, the new io locations are ram, rom,
and the hex digits.
2022-03-12 19:25:34 -06:00
Byron Lathi
3d9d340520
Get the FPGA part working
...
This changes some of the clocks, fixes a bug in the seven segment stuff.
2022-03-11 22:55:26 -06:00
Byron Lathi
cdf3da9b13
Add hex drivers
2022-03-11 18:25:55 -06:00
Byron Lathi
ad55f986f5
Add bb_spi_controller
...
Bit banged spi controller, very simple but very slow.
2022-03-08 15:26:01 -06:00
Byron Lathi
16b50dcca7
Add io chip select
2022-03-05 23:15:50 -06:00
Byron Lathi
c70272f9de
Add addr_decode and testbench
2022-03-05 20:11:47 -06:00
Byron Lathi
37e122197f
Refactor CI into one file
...
Remove the downstream stuff and consolidate the hw and sw pipelines into
one.
2022-03-05 19:22:00 -06:00
Byron Lathi
8855bedaf2
Change to directory before running quartus
2022-03-05 19:11:53 -06:00
Byron Lathi
e29bf45ecb
Add fpga ci
2022-03-05 19:00:06 -06:00
Byron Lathi
bc98b67ddf
Add boot rom
2022-03-05 18:12:27 -06:00
Byron Lathi
aca17a9cf8
Create quartus project
2022-03-05 17:52:42 -06:00
Byron Lathi
b996d93c99
Create quartus project
2022-03-05 16:38:12 -06:00
