Commit Graph

11 Commits

Author SHA1 Message Date
Byron Lathi
f99df72fe2 Update sdspi with write dma 2024-07-31 21:56:50 -07:00
Byron Lathi
383cb6d59e Add wait for DMA (should poll bit instead) 2024-07-26 22:58:31 -07:00
Byron Lathi
90c5c0dc94 Update SD version and start working on DMA 2024-07-21 18:58:35 -07:00
Byron Lathi
3d05d07541 Move shadow to us, get some commands going 2024-07-20 21:40:26 -07:00
Byron Lathi
f126e383a3 Update SD stuff 2024-07-20 16:03:06 -07:00
Byron Lathi
bdb3fc96d6 Add new sd wrapper
Wrapper is neccesary for the address offset and also because the
controller will trigger on reads/writes to registers, but we need access
to each byte of the 32 bit registers.

The wrapper will need to somehow chose when to actually trigger the
controller, maybe by having shadow registers?
2024-07-17 21:18:13 -07:00
Byron Lathi
25f51deaa7 Synthesize sd card dma 2024-03-17 22:26:42 -07:00
Byron Lathi
335f877d66 Run simulation with verilog sd emulator
This also slowed the cpu clock down, we should speed it up again
2024-03-14 08:17:05 -07:00
Byron Lathi
455814ec14 Update sd controller and test code 2024-03-12 18:20:51 -07:00
Byron Lathi
61f6e53327 Updates based on fpga test
1. in SD mode, CMD0 does not have a response, so we specifically ignore
   it.

2. The penable signal was messed up, although it looks like this doesn't
   matter anyway

3. The SD clock should be out of phase from the data signal by 180
   degrees, so that we get max hold time
2024-03-10 22:09:55 -07:00
Byron Lathi
da41e60ee7 integrate sd controller and super simple tb 2024-03-10 11:31:07 -07:00