Updates based on fpga test

1. in SD mode, CMD0 does not have a response, so we specifically ignore
   it.

2. The penable signal was messed up, although it looks like this doesn't
   matter anyway

3. The SD clock should be out of phase from the data signal by 180
   degrees, so that we get max hold time

sw/test_code/sd_controller_test/main.s

@@ -7,6 +7,7 @@
 .addr      _irq_int    ; IRQ/BRK vector
 
 SD_CONTROLLER = $e000
+SD_ARG = SD_CONTROLLER + $4
 CLK_DIV = $20
 
 .code
@@ -15,6 +16,16 @@ _nmi_int:
 _irq_int:
 
 _init:
+        lda #$00
+        sta SD_CONTROLLER
+
+        lda #$aa
+        sta SD_ARG
+        lda #$01
+        sta SD_ARG+1
+        lda #$00
+        sta SD_ARG+2
+        sta SD_ARG+3
         lda #$08
         sta SD_CONTROLLER