super6502

bslathi19/super6502

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Commit Graph

Author	SHA1	Message	Date
Byron Lathi	552fe8b6f8	Have valid crc when valid signal is present Previously the crc would be reset after 1 clock cycle while the valid signal was still high. Now the data is preserved in the valid state until the load signal is asserted.	2022-04-08 12:25:17 -05:00
Byron Lathi	e828df0807	Add crc7 module This module takes in a 40 bit word and generates the 7 bit crc7 appropriate for an SD card. It does not use any fancy parallel algorithm, it does it 1 bit at a time.	2022-04-08 00:50:28 -05:00

Author

SHA1

Message

Date

Byron Lathi

552fe8b6f8

Have valid crc when valid signal is present

Previously the crc would be reset after 1 clock cycle while the valid
signal was still high. Now the data is preserved in the valid state
until the load signal is asserted.

2022-04-08 12:25:17 -05:00

Byron Lathi

e828df0807

Add crc7 module

This module takes in a 40 bit word and generates the 7 bit crc7
appropriate for an SD card.

It does not use any fancy parallel algorithm, it does it 1 bit at a
time.

2022-04-08 00:50:28 -05:00

2 Commits