Have valid crc when valid signal is present

Previously the crc would be reset after 1 clock cycle while the valid
signal was still high. Now the data is preserved in the valid state
until the load signal is asserted.

hw/fpga/crc7.sv

@@ -95,6 +95,7 @@ always_comb begin
 
         VALID: begin
             valid =  ~load;
+            next_data = data;
             crc_out = data[6:0];
         end