Add tests for crc7

These are just some values that I found from an example program. This
does not test every possible value.

.gitlab-ci.yml

@@ -45,3 +45,10 @@ test_mm:
     script:
       - cd hw/fpga/simulation/modelsim/
       - vsim -do "do mm_testbench.do"
+
+test_crc7:
+    stage: test
+    image: bslathi19/modelsim_18.1:lite
+    script:
+      - cd hw/fpga/simulation/modelsim/
+      - vsim -do "do crc7_testbench.do"

hw/fpga/hvl/crc7_testbench.sv

@@ -0,0 +1,65 @@
+module testbench();
+
+timeunit 10ns;
+
+timeprecision 1ns;
+
+logic clk;
+logic rst;
+
+logic load;
+logic [39:0] data_in;
+
+logic [6:0] crc_out;
+logic valid;
+
+crc7 dut(.*);
+
+always #1 clk = clk === 1'b0;
+
+task create_sd_packet(logic [5:0] cmd, logic [31:0] data, output logic [47:0] _packet);
+    @(posedge clk);
+    data_in <= {1'b0, 1'b1, cmd, data};
+    load <= '1;
+    @(posedge clk);
+    load <= '0;
+
+    while (~valid) begin
+        //$display("Working %b", dut.data);
+        @(posedge clk);
+    end
+
+    _packet = {1'b0, 1'b1, cmd, data, crc_out, 1'b1};
+endtask
+
+logic [47:0] packet;
+
+initial begin
+    rst <= '1;
+    repeat(5) @(posedge clk);
+    rst <= '0;
+
+    create_sd_packet(6'h0, 32'h0, packet);
+    $display("Result: %x", packet);
+    assert(packet == 48'h400000000095) else
+        $error("Bad crc7. Got %x expected %x", packet, 48'h400000000095);
+
+    create_sd_packet(6'd8, 32'h1aa, packet);
+    $display("Result: %x", packet);
+    assert(packet == 48'h48000001aa87) else
+        $error("Bad crc7. Got %x expected %x", packet, 48'h48000001aa87);
+
+    create_sd_packet(6'd55, 32'h0, packet);
+    $display("Result: %x", packet);
+    assert(packet == 48'h770000000065) else
+        $error("Bad crc7. Got %x expected %x", packet, 48'h770000000065);
+        
+    create_sd_packet(6'd41, 32'h40180000, packet);
+    $display("Result: %x", packet);
+    assert(packet == 48'h694018000019) else
+        $error("Bad crc7. Got %x expected %x", packet, 48'h694018000019);
+
+    $finish();
+end
+
+endmodule

hw/fpga/simulation/modelsim/crc7_testbench.do

@@ -0,0 +1,23 @@
+transcript on
+if {[file exists rtl_work]} {
+	vdel -lib rtl_work -all
+}
+vlib rtl_work
+vmap work rtl_work
+
+vlog -sv -work work  {../../crc7.sv}
+vlog -sv -work work  {../../hvl/crc7_testbench.sv}
+
+vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L stratixv_ver -L stratixv_hssi_ver -L stratixv_pcie_hip_ver -L rtl_work -L work -voptargs="+acc"  testbench
+
+add wave -group {dut} -radix hexadecimal sim:/testbench/dut/*
+
+onfinish stop
+run -all
+
+if { [coverage attribute -name TESTSTATUS -concise] == "1"} {
+    echo Warning
+    quit -f -code 0
+}
+
+quit -code [coverage attribute -name TESTSTATUS -concise]