Byron Lathi 7ebbef487b Get a full tcp handshake, send data, and close cleanly

2024-10-01 21:38:17 -07:00

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cpu_wrapper

Add tcp regs and switch to verilator

2024-08-17 11:56:01 -07:00

interfaces @ 13c389dc18

Mega commit to kick things off

2024-09-01 22:23:21 -07:00

my-fifos @ a19156c9cd

M2S a TCP

2024-09-21 19:17:42 -07:00

network_processor

Get a full tcp handshake, send data, and close cleanly

2024-10-01 21:38:17 -07:00

rtl-common @ 1f071c11d9

Add tcp regs and switch to verilator

2024-08-17 11:56:01 -07:00

sd_controller_wrapper

Add tcp regs and switch to verilator

2024-08-17 11:56:01 -07:00

stream_dmas @ 92ef12aed9

update reg addr width, add fifo for m2s dma to write to

2024-09-02 14:48:57 -07:00

verilog-ethernet @ 2542187ec9

Add verilog ethernet

2024-08-19 17:40:16 -07:00

wb2axip @ 29e1e3755f

Add tcp regs and switch to verilator

2024-08-17 11:56:01 -07:00