Byron Lathi 04346ed625 Update .gitlab-ci.yml file ...

Add bootloader.hex as an artifact for the FPGA build

2022-04-19 20:05:53 +00:00

hw

Disable in system memory editor for ROM

2022-04-19 14:47:19 -05:00

sw

Replace bios with bootloader, don't use bootsector

2022-04-19 10:34:19 -05:00

.gitlab-ci.yml

Update .gitlab-ci.yml file

2022-04-19 20:05:53 +00:00

Description

No description provided

5.5 MiB

Languages

SystemVerilog 47.7%

Verilog 41.8%

Python 4.8%

VHDL 2%

Assembly 2%

Other 1.6%