Byron Lathi 16858bbb9d Register signals explicitly ...

These were previously inferred latches, but now that they are not, we
need to register them explicitly, otherwise they will be 0

2024-10-13 20:21:53 -07:00

..

constraints

Add mii clocks to constraints

2024-09-09 23:18:56 -07:00

ip/sdram_controller

Fix sdram sim

2024-03-03 21:33:28 -08:00

src

Register signals explicitly

2024-10-13 20:21:53 -07:00

.gitignore

Add tcp regs and switch to verilator

2024-08-17 11:56:01 -07:00

addr_map.mem

integrate sd controller and super simple tb

2024-03-10 11:31:07 -07:00

Makefile

Add program target to makefiles

2024-03-10 22:25:29 -07:00

sources.list

M2S a TCP

2024-09-21 19:17:42 -07:00

super6502_fpga.peri.xml

Reset renaming, set card_detect

2024-07-17 00:43:30 -07:00

super6502_fpga.xml

Increase TCP count to 2

2024-10-13 20:01:37 -07:00