Files
super6502/hw/fpga/hvl/sd_cmd_testbench.sv
Byron Lathi 50b0860137 Update testbench with more realistic timings
Updates the testbench to simulate writes with more correct timings.
Writes take two clock cycles since the cpu runs at half speed.
2022-04-10 17:50:49 -05:00

1.7 KiB