Byron Lathi 1b78f51933 Check all edge interrupts

2023-11-18 15:00:44 -08:00

doc

Update diagram again

2023-10-31 23:11:19 -07:00

hw

Check all edge interrupts

2023-11-18 15:00:44 -08:00

sw

Check all edge interrupts

2023-11-18 15:00:44 -08:00

.gitignore

Start spi controller and tb

2023-07-21 22:10:39 -07:00

.gitlab-ci.yml

Add irq code tb

2023-11-18 13:55:29 -08:00

.gitmodules

Resolve "Use dependencies instead of makefile chaining"

2023-09-30 04:16:52 +00:00

init_env.sh

Resolve "Run simulation as part of ci"

2023-09-30 05:05:12 +00:00

Description

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5.5 MiB

Languages

SystemVerilog 47.7%

Verilog 41.8%

Python 4.8%

VHDL 2%

Assembly 2%

Other 1.6%