Byron Lathi 236a75eef8 Update spi.s ...

Use names instead of magic values.

2022-03-10 11:29:32 -06:00

hw

Add bb_spi_controller

2022-03-08 15:26:01 -06:00

sw

Update spi.s

2022-03-10 11:29:32 -06:00

.gitlab-ci.yml

Add sim65 tests

2022-03-10 11:06:48 -06:00

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5.5 MiB

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SystemVerilog 47.7%

Verilog 41.8%

Python 4.8%

VHDL 2%

Assembly 2%

Other 1.6%