Byron Lathi 2600a23e59 Add memory_mapper testbench ...

This testbench simply creates the memory mapper, adds a mapping to the
first entry, and then makes sure the addresses are correct after
enabling and disabling the memory mapper.

2022-04-05 17:20:23 -05:00

hw

Add memory_mapper testbench

2022-04-05 17:20:23 -05:00

sw

Remove RAM memory section

2022-03-21 14:06:12 -05:00

.gitlab-ci.yml

Add platform generation to build stage

2022-03-17 14:25:26 -05:00

Description

No description provided

5.5 MiB

Languages

SystemVerilog 47.7%

Verilog 41.8%

Python 4.8%

VHDL 2%

Assembly 2%

Other 1.6%