bslathi19/super6502
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
83 Commits 10 Branches 0 Tags
264263b0d9d4eee03ef617e5ae8011743d951159
Go to file
Clone
Open with VS Code Open with VSCodium Open with Intellij IDEA
Download ZIP Download TAR.GZ Download BUNDLE
Byron Lathi 264263b0d9 Change "state" to "tx_state" etc.
2022-03-14 15:10:59 -05:00
hw
Change "state" to "tx_state" etc.
2022-03-14 15:10:59 -05:00
sw
Add UART interrupts
2022-03-14 14:57:45 -05:00
.gitlab-ci.yml
Update .gitlab-ci.yml
2022-03-10 22:27:43 +00:00
Description
No description provided
5.5 MiB
Languages
SystemVerilog 47.7%
Verilog 41.8%
Python 4.8%
VHDL 2%
Assembly 2%
Other 1.6%