Byron Lathi 264263b0d9 Change "state" to "tx_state" etc.

2022-03-14 15:10:59 -05:00

..

hvl

Add irq status register

2022-03-14 13:16:09 -05:00

output_files

Don't track vcd files either

2022-03-12 19:34:43 -06:00

simulation/modelsim

Add irq status register

2022-03-14 13:16:09 -05:00

.gitignore

Ignore greybox_tmp

2022-03-14 13:15:20 -05:00

addr_decode.sv

Add irq status register

2022-03-14 13:16:09 -05:00

bb_spi_controller.sv

Add bb_spi_controller

2022-03-08 15:26:01 -06:00

cpu_clk.ppf

Add hex drivers

2022-03-11 18:25:55 -06:00

cpu_clk.qip

Add hex drivers

2022-03-11 18:25:55 -06:00

cpu_clk.v

Add hex drivers

2022-03-11 18:25:55 -06:00

HexDriver.sv

Add hex drivers

2022-03-11 18:25:55 -06:00

ram.qip

Create quartus project

2022-03-05 17:52:42 -06:00

ram.v

Create quartus project

2022-03-05 17:52:42 -06:00

rom.qip

Add boot rom

2022-03-05 18:12:27 -06:00

rom.v

Get the FPGA part working

2022-03-11 22:55:26 -06:00

SevenSeg.sv

Implement enable byte in hw

2022-03-12 21:45:30 -06:00

super6502.qpf

Create quartus project

2022-03-05 16:38:12 -06:00

super6502.qsf

Connect Button 1 to cpu_irqb

2022-03-14 11:53:45 -05:00

super6502.sdc

Get the FPGA part working

2022-03-11 22:55:26 -06:00

super6502.sv

Add UART interrupts

2022-03-14 14:57:45 -05:00

uart.sv

Change "state" to "tx_state" etc.

2022-03-14 15:10:59 -05:00