163 lines
3.7 KiB
YAML
163 lines
3.7 KiB
YAML
# This file is a template, and might need editing before it works on your project.
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# This is a sample GitLab CI/CD configuration file that should run without any modifications.
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# It demonstrates a basic 3 stage CI/CD pipeline. Instead of real tests or scripts,
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# it uses echo commands to simulate the pipeline execution.
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#
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# A pipeline is composed of independent jobs that run scripts, grouped into stages.
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# Stages run in sequential order, but jobs within stages run in parallel.
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#
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# For more information, see: https://docs.gitlab.com/ee/ci/yaml/index.html#stages
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#
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# You can copy and paste this template into a new `.gitlab-ci.yml` file.
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# You should not add this template to an existing `.gitlab-ci.yml` file by using the `include:` keyword.
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#
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# To contribute improvements to CI/CD templates, please follow the Development guide at:
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# https://docs.gitlab.com/ee/development/cicd/templates.html
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# This specific template is located at:
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# https://gitlab.com/gitlab-org/gitlab/-/blob/master/lib/gitlab/ci/templates/Getting-Started.gitlab-ci.yml
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variables:
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GIT_SUBMODULE_STRATEGY: recursive
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stages: # List of stages for jobs, and their order of execution
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- toolchain
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- build
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- simulate
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build toolchain:
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tags:
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- linux
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stage: toolchain
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script:
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- source init_env.sh
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- cd sw/cc65
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- make -j
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artifacts:
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paths:
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- sw/cc65/bin
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- sw/cc65/lib
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build fpga: # This job runs in the build stage, which runs first.
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tags:
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- efinity
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- linux
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stage: build
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script:
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- source init_env.sh
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- cd hw/efinix_fpga
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- make
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build sim:
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tags:
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- iverilog
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- linux
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stage: build
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artifacts:
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paths:
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- hw/efinix_fpga/simulation/sim_top
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- hw/efinix_fpga/simulation/init_hex.mem
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script:
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- source init_env.sh
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- cd hw/efinix_fpga/simulation
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- make sim_top
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dependencies:
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- build toolchain
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build bios:
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tags:
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- linux
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stage: build
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script:
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- source init_env.sh
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- cd sw/
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- make bios
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dependencies:
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- build toolchain
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build kernel:
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tags:
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- linux
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stage: build
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script:
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- source init_env.sh
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- cd sw/
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- make kernel
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dependencies:
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- build toolchain
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run sim:
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tags:
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- linux
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- iverilog
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stage: simulate
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artifacts:
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paths:
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- hw/efinix_fpga/simulation/sim_top.vcd
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script:
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- source init_env.sh
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- cd hw/efinix_fpga/simulation
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- make sim
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dependencies:
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- build sim
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full sim:
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tags:
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- linux
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- iverilog
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stage: simulate
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artifacts:
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paths:
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- hw/efinix_fpga/simulation/sim_top.vcd
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- hw/efinix_fpga/simulation/fs.fat
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script:
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- source init_env.sh
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- cd hw/efinix_fpga/simulation
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- make clean
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- TEST_PROGRAM=$REPO_TOP/sw/bios/bios.hex TEST_FOLDER=$REPO_TOP/sw/bios make full_sim
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dependencies:
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- build toolchain
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mapper sim:
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tags:
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- linux
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- iverilog
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stage: simulate
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artifacts:
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paths:
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- hw/efinix_fpga/simulation/mapper_tb.vcd
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script:
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- source init_env.sh
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- cd hw/efinix_fpga/simulation
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- make clean
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- make mapper_tb
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- ./mapper_tb
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mapper_code sim:
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tags:
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- linux
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- iverilog
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stage: simulate
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artifacts:
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paths:
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- hw/efinix_fpga/simulation/mapper_code_tb.vcd
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script:
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- source init_env.sh
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- cd hw/efinix_fpga/simulation
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- make clean
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- TEST_PROGRAM_NAME=mapper_test make mapper_code_tb
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- ./mapper_code_tb
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interrupt_controller sim:
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tags:
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- linux
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- iverilog
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stage: simulate
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artifacts:
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paths:
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- hw/efinix_fpga/simulation/interrupt_controller.vcd
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script:
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- source init_env.sh
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- cd hw/efinix_fpga/simulation
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- make clean
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- TEST_PROGRAM_NAME=mapper_test make interrupt_controller_tb
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- ./interrupt_controller_tb |