Byron Lathi
5d4bad80a2
Fix level triggered test, add to ci
2023-11-16 08:14:58 -08:00
Byron Lathi
e3ae984177
Upload filesystem image as well
2023-10-26 20:40:00 -07:00
Byron Lathi
5f863c9857
Add code testbench
2023-10-21 17:07:43 -07:00
Byron Lathi
e621d4047b
Add mapper and testbench
2023-10-16 23:45:33 -07:00
Byron Lathi
4988d458b7
full sim requires toolchain
2023-10-11 01:02:41 -07:00
Byron Lathi
d3ea5ed4d1
Use udisksctl
2023-10-11 00:59:41 -07:00
Byron Lathi
cc32430f2a
Refactor makefile, update verilog-sd-emulator
2023-09-29 23:48:28 -07:00
Byron Lathi
f8bdbfbb2b
Resolve "Run simulation as part of ci"
2023-09-30 05:05:12 +00:00
Byron Lathi
d3d3fea916
Resolve "Use dependencies instead of makefile chaining"
2023-09-30 04:16:52 +00:00
Byron Lathi
62967aa88d
Resolve "Add build check to CI"
2023-09-29 05:14:52 +00:00
Byron Lathi
df89962932
remove env call
2023-09-28 21:34:42 -07:00
Byron Lathi
59f88ead3f
Update .gitlab-ci.yml file
2023-09-29 04:25:54 +00:00
Byron Lathi
366c6c9b6e
Remove gitlab ci
2022-12-20 17:29:15 -05:00
Byron Lathi
6e650e627f
Change CI to ignore fpga build, kicad to symlink
...
Did not automate tests with efinix yet.
2022-10-04 17:25:42 -05:00
Byron Lathi
9de3c5b1fa
update ci
2022-04-20 12:49:23 -05:00
Byron Lathi
0e98f7536b
update ci
2022-04-20 12:46:45 -05:00
Byron Lathi
aa717685e3
Use our own toolchain instead of the one in the image
...
Now that we are adding our own target we can compile our own toolchain
instead of using the stock one. This does mean that there isn't really a
purpose to using the alpine cc65 image though
2022-04-20 12:41:20 -05:00
Byron Lathi
c7ff69a1a0
Update .gitlab-ci.yml file
2022-04-19 20:30:27 +00:00
Byron Lathi
7b84d8a9c2
Update .gitlab-ci.yml file
2022-04-19 20:27:25 +00:00
Byron Lathi
25883aa3cc
Update .gitlab-ci.yml file
2022-04-19 20:09:32 +00:00
Byron Lathi
bd748cab86
Update .gitlab-ci.yml file
2022-04-19 20:08:10 +00:00
Byron Lathi
04346ed625
Update .gitlab-ci.yml file
...
Add bootloader.hex as an artifact for the FPGA build
2022-04-19 20:05:53 +00:00
Byron Lathi
6844c48a3b
Update ci
2022-04-16 22:07:19 -05:00
Byron Lathi
8495f1f002
Update ci
2022-04-16 22:02:18 -05:00
Byron Lathi
38566f7b4a
add testbench for SD command tx
...
Sends a few commands which we know the proper checksum for and makes
sure that the bits on the output are correct.
2022-04-08 12:29:15 -05:00
Byron Lathi
3e69109474
Add tests for crc7
...
These are just some values that I found from an example program. This
does not test every possible value.
2022-04-08 00:56:14 -05:00
Byron Lathi
3c44be8e6d
Add mm_testbench to gitlab-ci
2022-04-05 17:31:24 -05:00
Byron Lathi
ee97c4cbaa
Add platform generation to build stage
2022-03-17 14:25:26 -05:00
Byron Lathi
254d7b887e
Update .gitlab-ci.yml
2022-03-10 22:27:43 +00:00
Byron Lathi
6f3155cf35
Add sim65 tests
2022-03-10 11:06:48 -06:00
Byron Lathi
ad55f986f5
Add bb_spi_controller
...
Bit banged spi controller, very simple but very slow.
2022-03-08 15:26:01 -06:00
Byron Lathi
0ad18720bb
update cc65 docker image
2022-03-05 22:58:53 -06:00
Byron Lathi
db3a150f93
Use different cc65 docker image
2022-03-05 22:39:36 -06:00
Byron Lathi
378b3c0cb1
run addr_decode test
2022-03-05 20:13:33 -06:00
Byron Lathi
37e122197f
Refactor CI into one file
...
Remove the downstream stuff and consolidate the hw and sw pipelines into
one.
2022-03-05 19:22:00 -06:00
Byron Lathi
397372d9dc
Revert "Change to using includes rather than children"
...
This reverts commit fd87d5b0ba
2022-03-06 01:09:37 +00:00
Byron Lathi
fd87d5b0ba
Change to using includes rather than children
2022-03-05 19:08:42 -06:00
Byron Lathi
a854ac4067
Fix fpga ci
...
typo
2022-03-05 19:00:49 -06:00
Byron Lathi
e29bf45ecb
Add fpga ci
2022-03-05 19:00:06 -06:00
Byron Lathi
dbf990df3b
Add ci
2022-03-05 18:57:19 -06:00
