add testbench for SD command tx

Sends a few commands which we know the proper checksum for and makes
sure that the bits on the output are correct.

.gitlab-ci.yml

@@ -52,3 +52,10 @@ test_crc7:
     script:
       - cd hw/fpga/simulation/modelsim/
       - vsim -do "do crc7_testbench.do"
+
+test_sd_cmd:
+    stage: test
+    image: bslathi19/modelsim_18.1:lite
+    script:
+      - cd hw/fpga/simulation/modelsim/
+      - vsim -do "sd_cmd_testbench.do"

hw/fpga/hvl/sd_cmd_testbench.sv

@@ -0,0 +1,74 @@
+module testbench();
+
+timeunit 10ns;
+
+timeprecision 1ns;
+
+logic clk;
+logic clk_50;
+logic rst;
+
+logic [3:0] addr;
+logic [7:0] data;
+logic cs;
+
+logic i_sd_cmd;
+logic o_sd_cmd;
+
+logic i_sd_data;
+logic o_sd_dat;
+
+sd_controller dut(.*);
+
+always #1 clk_50 = clk_50 === 1'b0;
+always #100 clk = clk === 1'b0;
+
+task write_reg(logic [3:0] _addr, logic [7:0] _data);
+    @(negedge clk);
+    cs <= '1;
+    addr <= _addr;
+    data <= _data;
+    @(posedge clk);
+    cs <= '0;
+    @(negedge clk);
+endtask
+
+task verify_cmd(logic [5:0] cmd, logic [31:0] arg, logic [47:0] verify);
+    write_reg(0, arg[7:0]);
+    write_reg(1, arg[15:8]);
+    write_reg(2, arg[23:16]);
+    write_reg(3, arg[31:24]);
+    write_reg(4, cmd);
+
+    @(posedge clk);
+    @(posedge clk);
+
+    while (dut.state.macro == dut.TXCMD) begin
+        assert(o_sd_cmd == verify[47-dut.state.count]) else begin
+            $error("cmd output error: Expected %h:%b, got %h:%b", 
+                47-dut.state.count, verify[47-dut.state.count],
+                47-dut.state.count, o_sd_cmd);
+        end
+        @(negedge clk);
+    end
+endtask
+
+localparam cmd0 = 48'h400000000095;
+localparam cmd8 = 48'h48000001aa87;
+localparam cmd55 = 48'h770000000065;
+localparam cmd41 = 48'h694018000019;
+
+initial begin
+    rst <= '1;
+    repeat(5) @(posedge clk);
+    rst <= '0;
+
+    verify_cmd(0, 0, cmd0);
+    verify_cmd(8, 'h1aa, cmd8);
+    verify_cmd('d55, 0, cmd55);
+    verify_cmd('d41, 'h40180000, cmd41);
+
+    $finish();
+end
+
+endmodule

hw/fpga/simulation/modelsim/sd_cmd_testbench.do

@@ -0,0 +1,24 @@
+transcript on
+if {[file exists rtl_work]} {
+	vdel -lib rtl_work -all
+}
+vlib rtl_work
+vmap work rtl_work
+
+vlog -sv -work work  {../../sd_controller.sv}
+vlog -sv -work work  {../../crc7.sv}
+vlog -sv -work work  {../../hvl/sd_cmd_testbench.sv}
+
+vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L stratixv_ver -L stratixv_hssi_ver -L stratixv_pcie_hip_ver -L rtl_work -L work -voptargs="+acc"  testbench
+
+add wave -group {dut} -radix hexadecimal sim:/testbench/dut/*
+
+onfinish stop
+run -all
+
+if { [coverage attribute -name TESTSTATUS -concise] == "1"} {
+    echo Warning
+    quit -f -code 0
+}
+
+quit -code [coverage attribute -name TESTSTATUS -concise]