bslathi19/super6502
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2d49fe22a708fdd33cc8cd12e2c302b5a14aa79c
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Byron Lathi 2d49fe22a7 ignore .sopcinfo 
This will be generated automatically when built.
2022-03-17 13:53:07 -05:00
hw
ignore .sopcinfo
2022-03-17 13:53:07 -05:00
sw
Create SDRAM memory region
2022-03-17 13:37:34 -05:00
.gitlab-ci.yml
Update .gitlab-ci.yml
2022-03-10 22:27:43 +00:00
Description
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5.5 MiB
Languages
SystemVerilog 47.7%
Verilog 41.8%
Python 4.8%
VHDL 2%
Assembly 2%
Other 1.6%