Byron Lathi 44b324a768 Change drill output folder

2022-10-12 18:51:40 -05:00

hw

Change drill output folder

2022-10-12 18:51:40 -05:00

sw

Throw everything up

2022-10-04 17:15:49 -05:00

.gitlab-ci.yml

Change CI to ignore fpga build, kicad to symlink

2022-10-04 17:25:42 -05:00

.gitmodules

Use our own toolchain instead of the one in the image

2022-04-20 12:41:20 -05:00

Description

No description provided

5.5 MiB

Languages

SystemVerilog 47.7%

Verilog 41.8%

Python 4.8%

VHDL 2%

Assembly 2%

Other 1.6%