Byron Lathi 4d0abbb508 Add sim uart

2023-09-27 22:15:27 -07:00

hw

Add sim uart

2023-09-27 22:15:27 -07:00

sw

New test program that causes the error

2023-09-26 18:23:01 -07:00

.gitignore

Start spi controller and tb

2023-07-21 22:10:39 -07:00

.gitmodules

Add submodule back

2023-09-23 09:59:39 -07:00

init_env.sh

Add REPO_TOP env var

2023-09-24 10:35:17 -07:00

Description

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5.5 MiB

Languages

SystemVerilog 47.7%

Verilog 41.8%

Python 4.8%

VHDL 2%

Assembly 2%

Other 1.6%