Byron Lathi 552fe8b6f8 Have valid crc when valid signal is present ...

Previously the crc would be reset after 1 clock cycle while the valid
signal was still high. Now the data is preserved in the valid state
until the load signal is asserted.

2022-04-08 12:25:17 -05:00

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board

Ignore gerber output files and folders

2022-03-08 15:25:05 -06:00

fpga

Have valid crc when valid signal is present

2022-04-08 12:25:17 -05:00