Byron Lathi 5560b06c9f Merge branch 'uart' into 'master' ...

Add UART TX Module

See merge request bslathi19/super6502!3

2022-03-14 16:02:04 +00:00

hw

Update cs_testbench.sv

2022-03-14 10:56:15 -05:00

sw

Add sample puts function

2022-03-14 10:46:36 -05:00

.gitlab-ci.yml

Update .gitlab-ci.yml

2022-03-10 22:27:43 +00:00

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5.5 MiB

Languages

SystemVerilog 47.7%

Verilog 41.8%

Python 4.8%

VHDL 2%

Assembly 2%

Other 1.6%