bslathi19/super6502
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Byron Lathi 5834f179d2 Ignore more modelsim files 
Ignore all bak files and msim_transcript
2022-03-13 19:39:14 -05:00
hw
Ignore more modelsim files
2022-03-13 19:39:14 -05:00
sw
Update Makefile
2022-03-12 22:40:48 -06:00
.gitlab-ci.yml
Update .gitlab-ci.yml
2022-03-10 22:27:43 +00:00
Description
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5.5 MiB
Languages
SystemVerilog 47.7%
Verilog 41.8%
Python 4.8%
VHDL 2%
Assembly 2%
Other 1.6%