Byron Lathi 5c72c574e5 Change link file to output flat binary

2022-04-21 17:37:12 -05:00

hw

Disable in system memory editor for ROM

2022-04-19 14:47:19 -05:00

sw

Change link file to output flat binary

2022-04-21 17:37:12 -05:00

.gitlab-ci.yml

update ci

2022-04-20 12:49:23 -05:00

.gitmodules

Use our own toolchain instead of the one in the image

2022-04-20 12:41:20 -05:00

Description

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5.5 MiB

Languages

SystemVerilog 47.7%

Verilog 41.8%

Python 4.8%

VHDL 2%

Assembly 2%

Other 1.6%