87 lines
2.6 KiB
Systemverilog
87 lines
2.6 KiB
Systemverilog
module sdram(
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input rst,
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input clk_50,
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input cpu_clk,
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input [15:0] addr,
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input sdram_cs,
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input rwb,
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input [7:0] data_in,
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output [7:0] data_out,
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///////// SDRAM /////////
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output wire DRAM_CLK,
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output wire DRAM_CKE,
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output wire [12: 0] DRAM_ADDR,
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output wire [ 1: 0] DRAM_BA,
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inout wire [15: 0] DRAM_DQ,
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output wire DRAM_LDQM,
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output wire DRAM_UDQM,
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output wire DRAM_CS_N,
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output wire DRAM_WE_N,
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output wire DRAM_CAS_N,
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output wire DRAM_RAS_N
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);
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enum logic {ACCESS, WAIT } state, next_state;
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logic ack;
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logic _sdram_cs;
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always @(posedge clk_50) begin
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if (rst)
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state <= ACCESS;
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else
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state <= next_state;
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end
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always_comb begin
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next_state = state;
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case (state)
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ACCESS: begin
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if (sdram_cs & ~rwb & ack)
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next_state = WAIT;
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end
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WAIT: begin
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if (~cpu_clk)
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next_state = ACCESS;
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end
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endcase
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end
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always_comb begin
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_sdram_cs = '0;
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case (state)
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ACCESS: begin
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_sdram_cs = sdram_cs & cpu_clk;
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end
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WAIT: begin
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_sdram_cs = '0;
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end
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endcase
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end
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sdram_platform u0 (
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.clk_clk (clk_50), // clk.clk
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.reset_reset_n (1'b1), // reset.reset_n
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.ext_bus_address (addr), // ext_bus.address
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.ext_bus_byte_enable (1'b1), // .byte_enable
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.ext_bus_read (_sdram_cs & rwb), // .read
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.ext_bus_write (_sdram_cs & ~rwb), // .write
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.ext_bus_write_data (data_in), // .write_data
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.ext_bus_acknowledge (ack), // .acknowledge
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.ext_bus_read_data (data_out), // .read_data
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//SDRAM
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.sdram_clk_clk(DRAM_CLK), //clk_sdram.clk
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.sdram_wire_addr(DRAM_ADDR), //sdram_wire.addr
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.sdram_wire_ba(DRAM_BA), //.ba
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.sdram_wire_cas_n(DRAM_CAS_N), //.cas_n
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.sdram_wire_cke(DRAM_CKE), //.cke
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.sdram_wire_cs_n(DRAM_CS_N), //.cs_n
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.sdram_wire_dq(DRAM_DQ), //.dq
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.sdram_wire_dqm({DRAM_UDQM,DRAM_LDQM}), //.dqm
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.sdram_wire_ras_n(DRAM_RAS_N), //.ras_n
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.sdram_wire_we_n(DRAM_WE_N) //.we_n
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);
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endmodule |