bslathi19/super6502
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791bffb248d0056d6af03e0cfdcaeb3fe6d67ca5
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Byron Lathi 791bffb248 Add copy data back
2023-09-04 14:08:52 -07:00
hw
Add copy data back
2023-09-04 14:08:52 -07:00
sw
Add copy data back
2023-09-04 14:08:52 -07:00
.gitignore
Start spi controller and tb
2023-07-21 22:10:39 -07:00
.gitmodules
Use our own toolchain instead of the one in the image
2022-04-20 12:41:20 -05:00
Description
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5.5 MiB
Languages
SystemVerilog 47.7%
Verilog 41.8%
Python 4.8%
VHDL 2%
Assembly 2%
Other 1.6%