Files
super6502/hw/fpga/simulation/modelsim/uart.do
Byron Lathi b48438f6b2 Add write and puts tasks to the uart testbench
The write task will transmit a single byte, the puts task will transmit
a string of length n. These do not do any verification, you still have
to look at the output.
2022-03-14 00:04:04 -05:00

18 lines
479 B
Plaintext

transcript on
if {[file exists rtl_work]} {
vdel -lib rtl_work -all
}
vlib rtl_work
vmap work rtl_work
vlog -sv -work work {../../uart.sv}
vlog -sv -work work {../../hvl/uart_testbench.sv}
vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L stratixv_ver -L stratixv_hssi_ver -L stratixv_pcie_hip_ver -L rtl_work -L work -voptargs="+acc" testbench
add wave -group {dut} -radix hexadecimal sim:/testbench/dut/*
onfinish stop
run -all