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8495f1f002a5f19a65e50c32c8b8699bc9f8226c
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Byron Lathi 8495f1f002 Update ci
2022-04-16 22:02:18 -05:00
hw
Reset bit count upon entering RXDATA
2022-04-14 11:20:48 -05:00
sw
Separate kernel code from test code
2022-04-16 21:58:37 -05:00
.gitlab-ci.yml
Update ci
2022-04-16 22:02:18 -05:00
Description
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5.5 MiB
Languages
SystemVerilog 47.7%
Verilog 41.8%
Python 4.8%
VHDL 2%
Assembly 2%
Other 1.6%