83 lines
2.4 KiB
Markdown
83 lines
2.4 KiB
Markdown
# RTC
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## Overview
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The RTC is capable of keeping track of elapsed time as well as generating
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periodic interrupts. Its input frequency is (currently) the same as the CPU
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frequency. The architecture is shown below:
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The `counter` register is a 32 bit register which increments by `increment`
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every clock tick. When this value reaches `threshold`, both `output` and
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`irq_counter` are incremented by 1. When `irq_counter` reaches `irq_threshold`,
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an interrupt is generated.
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The interrupt frequency can be calculated with the following equations:
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$$ F_{out}=\frac{F_{in}\cdot{increment}}{threshold} $$
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$$ F_{irq}=\frac{F_{out}}{irq\_threshold} $$
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Where $ F_{out} $ is the frequency at which the output changes and $ F_{irq} $
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is the frequency at which interrupts occur.
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## Interface
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The RTC is controlled through two 8-bit registers, `CMD` and `DAT`.
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The upepr 4 bits of `CMD` control which register is accessed, and the lower 4
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bits control the byte select. The RTC uses 32 bit registers, so only values of
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0-3 are supported.
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### CMD
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| [7:4] | [3:2 | [1:0] |
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|------------------ |---------- |------------- |
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| Register Address | Reserved | Byte Select |
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### DAT
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| [7:0] |
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|----------------------- |
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| Data[8*Byte_sel +: 8] |
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## Registers
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### Register Map
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| Address | Read | Write |
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|--------- |--------------- |--------------- |
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| 0 | Threshold | Threshold |
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| 1 | Increment | Increment |
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| 2 | IRQ Threshold | IRQ Threshold |
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| 3 | Output | Control |
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### Threshold
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32 bit threshold register. When `counter` reaches this value, `output` and
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`irq_counter` are incremented by 1, and `counter` is reset back to 0.
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### Increment
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32 bit increment register. Every clock cycle, `counter` is incremented by
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`increment`
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### IRQ Threshold
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32 bit IRQ threshold register. When `irq_counter` reaches this value, and IRQ
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is generated and `irq_counter` is reset back to 0.
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### Output
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32 bit output register. This value ticks up.
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### Control
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| [7:2] | [1] | [0] |
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|---------- |------------ |-------- |
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| Reserved | IRQ Enable | Enable |
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8 bit Control register. Regardless of Byte Select, any write to address 3 will
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write to this register. `IRQ Enable` controls interrupt generation. `Enable` is
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a global enable. When 0, all counter registers are set to 0.
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