Byron Lathi ac3f5a0fca Merge branch 'uart-irq' into 'master' ...

Add UART Receive logic

See merge request bslathi19/super6502!5

2022-03-14 21:56:27 +00:00

hw

Add receive logic to UART

2022-03-14 16:41:59 -05:00

sw

Add uart_rxb

2022-03-14 16:48:24 -05:00

.gitlab-ci.yml

Update .gitlab-ci.yml

2022-03-10 22:27:43 +00:00

Description

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5.5 MiB

Languages

SystemVerilog 47.7%

Verilog 41.8%

Python 4.8%

VHDL 2%

Assembly 2%

Other 1.6%